1 /*
2 *
3 * hda_intel.c - Implementation of primary alsa driver code base
4 * for Intel HD Audio.
5 *
6 * Copyright(c) 2004 Intel Corporation. All rights reserved.
7 *
8 * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
9 * PeiSen Hou <pshou@realtek.com.tw>
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the Free
13 * Software Foundation; either version 2 of the License, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful, but WITHOUT
17 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
18 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
19 * more details.
20 *
21 * You should have received a copy of the GNU General Public License along with
22 * this program; if not, write to the Free Software Foundation, Inc., 59
23 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
24 *
25 * CONTACTS:
26 *
27 * Matt Jared matt.jared@intel.com
28 * Andy Kopp andy.kopp@intel.com
29 * Dan Kogan dan.d.kogan@intel.com
30 *
31 * CHANGES:
32 *
33 * 2004.12.01 Major rewrite by tiwai, merged the work of pshou
34 *
35 */
36
37 #include <sound/driver.h>
38 #include <asm/io.h>
39 #include <linux/delay.h>
40 #include <linux/interrupt.h>
41 #include <linux/kernel.h>
42 #include <linux/module.h>
43 #include <linux/dma-mapping.h>
44 #include <linux/moduleparam.h>
45 #include <linux/init.h>
46 #include <linux/slab.h>
47 #include <linux/pci.h>
48 #include <linux/mutex.h>
49 #include <sound/core.h>
50 #include <sound/initval.h>
51 #include "hda_codec.h"
52
53
54 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
55 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
56 static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
57 static char *model[SNDRV_CARDS];
58 static int position_fix[SNDRV_CARDS];
59 static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
60 static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
61 static int single_cmd;
62 static int enable_msi;
63
64 module_param_array(index, int, NULL, 0444);
65 MODULE_PARM_DESC(index, "Index value for Intel HD audio interface.");
66 module_param_array(id, charp, NULL, 0444);
67 MODULE_PARM_DESC(id, "ID string for Intel HD audio interface.");
68 module_param_array(enable, bool, NULL, 0444);
69 MODULE_PARM_DESC(enable, "Enable Intel HD audio interface.");
70 module_param_array(model, charp, NULL, 0444);
71 MODULE_PARM_DESC(model, "Use the given board model.");
72 module_param_array(position_fix, int, NULL, 0444);
73 MODULE_PARM_DESC(position_fix, "Fix DMA pointer "
74 "(0 = auto, 1 = none, 2 = POSBUF).");
75 module_param_array(bdl_pos_adj, int, NULL, 0644);
76 MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset.");
77 module_param_array(probe_mask, int, NULL, 0444);
78 MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1).");
79 module_param(single_cmd, bool, 0444);
80 MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs "
81 "(for debugging only).");
82 module_param(enable_msi, int, 0444);
83 MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)");
84
85 #ifdef CONFIG_SND_HDA_POWER_SAVE
86 /* power_save option is defined in hda_codec.c */
87
88 /* reset the HD-audio controller in power save mode.
89 * this may give more power-saving, but will take longer time to
90 * wake up.
91 */
92 static int power_save_controller = 1;
93 module_param(power_save_controller, bool, 0644);
94 MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode.");
95 #endif
96
97 MODULE_LICENSE("GPL");
98 MODULE_SUPPORTED_DEVICE("{{Intel, ICH6},"
99 "{Intel, ICH6M},"
100 "{Intel, ICH7},"
101 "{Intel, ESB2},"
102 "{Intel, ICH8},"
103 "{Intel, ICH9},"
104 "{Intel, ICH10},"
105 "{Intel, PCH},"
106 "{Intel, SCH},"
107 "{ATI, SB450},"
108 "{ATI, SB600},"
109 "{ATI, RS600},"
110 "{ATI, RS690},"
111 "{ATI, RS780},"
112 "{ATI, R600},"
113 "{ATI, RV630},"
114 "{ATI, RV610},"
115 "{ATI, RV670},"
116 "{ATI, RV635},"
117 "{ATI, RV620},"
118 "{ATI, RV770},"
119 "{VIA, VT8251},"
120 "{VIA, VT8237A},"
121 "{SiS, SIS966},"
122 "{ULI, M5461}}");
123 MODULE_DESCRIPTION("Intel HDA driver");
124
125 #define SFX "hda-intel: "
126
127
128 /*
129 * registers
130 */
131 #define ICH6_REG_GCAP 0x00
132 #define ICH6_REG_VMIN 0x02
133 #define ICH6_REG_VMAJ 0x03
134 #define ICH6_REG_OUTPAY 0x04
135 #define ICH6_REG_INPAY 0x06
136 #define ICH6_REG_GCTL 0x08
137 #define ICH6_REG_WAKEEN 0x0c
138 #define ICH6_REG_STATESTS 0x0e
139 #define ICH6_REG_GSTS 0x10
140 #define ICH6_REG_INTCTL 0x20
141 #define ICH6_REG_INTSTS 0x24
142 #define ICH6_REG_WALCLK 0x30
143 #define ICH6_REG_SYNC 0x34
144 #define ICH6_REG_CORBLBASE 0x40
145 #define ICH6_REG_CORBUBASE 0x44
146 #define ICH6_REG_CORBWP 0x48
147 #define ICH6_REG_CORBRP 0x4A
148 #define ICH6_REG_CORBCTL 0x4c
149 #define ICH6_REG_CORBSTS 0x4d
150 #define ICH6_REG_CORBSIZE 0x4e
151
152 #define ICH6_REG_RIRBLBASE 0x50
153 #define ICH6_REG_RIRBUBASE 0x54
154 #define ICH6_REG_RIRBWP 0x58
155 #define ICH6_REG_RINTCNT 0x5a
156 #define ICH6_REG_RIRBCTL 0x5c
157 #define ICH6_REG_RIRBSTS 0x5d
158 #define ICH6_REG_RIRBSIZE 0x5e
159
160 #define ICH6_REG_IC 0x60
161 #define ICH6_REG_IR 0x64
162 #define ICH6_REG_IRS 0x68
163 #define ICH6_IRS_VALID (1<<1)
164 #define ICH6_IRS_BUSY (1<<0)
165
166 #define ICH6_REG_DPLBASE 0x70
167 #define ICH6_REG_DPUBASE 0x74
168 #define ICH6_DPLBASE_ENABLE 0x1 /* Enable position buffer */
169
170 /* SD offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
171 enum { SDI0, SDI1, SDI2, SDI3, SDO0, SDO1, SDO2, SDO3 };
172
173 /* stream register offsets from stream base */
174 #define ICH6_REG_SD_CTL 0x00
175 #define ICH6_REG_SD_STS 0x03
176 #define ICH6_REG_SD_LPIB 0x04
177 #define ICH6_REG_SD_CBL 0x08
178 #define ICH6_REG_SD_LVI 0x0c
179 #define ICH6_REG_SD_FIFOW 0x0e
180 #define ICH6_REG_SD_FIFOSIZE 0x10
181 #define ICH6_REG_SD_FORMAT 0x12
182 #define ICH6_REG_SD_BDLPL 0x18
183 #define ICH6_REG_SD_BDLPU 0x1c
184
185 /* PCI space */
186 #define ICH6_PCIREG_TCSEL 0x44
187
188 /*
189 * other constants
190 */
191
192 /* max number of SDs */
193 /* ICH, ATI and VIA have 4 playback and 4 capture */
194 #define ICH6_NUM_CAPTURE 4
195 #define ICH6_NUM_PLAYBACK 4
196
197 /* ULI has 6 playback and 5 capture */
198 #define ULI_NUM_CAPTURE 5
199 #define ULI_NUM_PLAYBACK 6
200
201 /* ATI HDMI has 1 playback and 0 capture */
202 #define ATIHDMI_NUM_CAPTURE 0
203 #define ATIHDMI_NUM_PLAYBACK 1
204
205 /* TERA has 4 playback and 3 capture */
206 #define TERA_NUM_CAPTURE 3
207 #define TERA_NUM_PLAYBACK 4
208
209 /* this number is statically defined for simplicity */
210 #define MAX_AZX_DEV 16
211
212 /* max number of fragments - we may use more if allocating more pages for BDL */
213 #define BDL_SIZE 4096
214 #define AZX_MAX_BDL_ENTRIES (BDL_SIZE / 16)
215 #define AZX_MAX_FRAG 32
216 /* max buffer size - no h/w limit, you can increase as you like */
217 #define AZX_MAX_BUF_SIZE (1024*1024*1024)
218 /* max number of PCM devics per card */
219 #define AZX_MAX_PCMS 8
220
221 /* RIRB int mask: overrun[2], response[0] */
222 #define RIRB_INT_RESPONSE 0x01
223 #define RIRB_INT_OVERRUN 0x04
224 #define RIRB_INT_MASK 0x05
225
226 /* STATESTS int mask: SD2,SD1,SD0 */
227 #define AZX_MAX_CODECS 3
228 #define STATESTS_INT_MASK 0x07
229
230 /* SD_CTL bits */
231 #define SD_CTL_STREAM_RESET 0x01 /* stream reset bit */
232 #define SD_CTL_DMA_START 0x02 /* stream DMA start bit */
233 #define SD_CTL_STRIPE (3 << 16) /* stripe control */
234 #define SD_CTL_TRAFFIC_PRIO (1 << 18) /* traffic priority */
235 #define SD_CTL_DIR (1 << 19) /* bi-directional stream */
236 #define SD_CTL_STREAM_TAG_MASK (0xf << 20)
237 #define SD_CTL_STREAM_TAG_SHIFT 20
238
239 /* SD_CTL and SD_STS */
240 #define SD_INT_DESC_ERR 0x10 /* descriptor error interrupt */
241 #define SD_INT_FIFO_ERR 0x08 /* FIFO error interrupt */
242 #define SD_INT_COMPLETE 0x04 /* completion interrupt */
243 #define SD_INT_MASK (SD_INT_DESC_ERR|SD_INT_FIFO_ERR|\
244 SD_INT_COMPLETE)
245
246 /* SD_STS */
247 #define SD_STS_FIFO_READY 0x20 /* FIFO ready */
248
249 /* INTCTL and INTSTS */
250 #define ICH6_INT_ALL_STREAM 0xff /* all stream interrupts */
251 #define ICH6_INT_CTRL_EN 0x40000000 /* controller interrupt enable bit */
252 #define ICH6_INT_GLOBAL_EN 0x80000000 /* global interrupt enable bit */
253
254 /* GCTL unsolicited response enable bit */
255 #define ICH6_GCTL_UREN (1<<8)
256
257 /* GCTL reset bit */
258 #define ICH6_GCTL_RESET (1<<0)
259
260 /* CORB/RIRB control, read/write pointer */
261 #define ICH6_RBCTL_DMA_EN 0x02 /* enable DMA */
262 #define ICH6_RBCTL_IRQ_EN 0x01 /* enable IRQ */
263 #define ICH6_RBRWP_CLR 0x8000 /* read/write pointer clear */
264 /* below are so far hardcoded - should read registers in future */
265 #define ICH6_MAX_CORB_ENTRIES 256
266 #define ICH6_MAX_RIRB_ENTRIES 256
267
268 /* position fix mode */
269 enum {
270 POS_FIX_AUTO,
271 POS_FIX_LPIB,
272 POS_FIX_POSBUF,
273 };
274
275 /* Defines for ATI HD Audio support in SB450 south bridge */
276 #define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR 0x42
277 #define ATI_SB450_HDAUDIO_ENABLE_SNOOP 0x02
278
279 /* Defines for Nvidia HDA support */
280 #define NVIDIA_HDA_TRANSREG_ADDR 0x4e
281 #define NVIDIA_HDA_ENABLE_COHBITS 0x0f
282
283 /* Defines for Intel SCH HDA snoop control */
284 #define INTEL_SCH_HDA_DEVC 0x78
285 #define INTEL_SCH_HDA_DEVC_NOSNOOP (0x1<<11)
286
287
288 /*
289 */
290
291 struct azx_dev {
292 struct snd_dma_buffer bdl; /* BDL buffer */
293 u32 *posbuf; /* position buffer pointer */
294
295 unsigned int bufsize; /* size of the play buffer in bytes */
296 unsigned int period_bytes; /* size of the period in bytes */
297 unsigned int frags; /* number for period in the play buffer */
298 unsigned int fifo_size; /* FIFO size */
299
300 void __iomem *sd_addr; /* stream descriptor pointer */
301
302 u32 sd_int_sta_mask; /* stream int status mask */
303
304 /* pcm support */
305 struct snd_pcm_substream *substream; /* assigned substream,
306 * set in PCM open
307 */
308 unsigned int format_val; /* format value to be set in the
309 * controller and the codec
310 */
311 unsigned char stream_tag; /* assigned stream */
312 unsigned char index; /* stream index */
313
314 unsigned int opened :1;
315 unsigned int running :1;
316 unsigned int irq_pending :1;
317 unsigned int irq_ignore :1;
318 };
319
320 /* CORB/RIRB */
321 struct azx_rb {
322 u32 *buf; /* CORB/RIRB buffer
323 * Each CORB entry is 4byte, RIRB is 8byte
324 */
325 dma_addr_t addr; /* physical address of CORB/RIRB buffer */
326 /* for RIRB */
327 unsigned short rp, wp; /* read/write pointers */
328 int cmds; /* number of pending requests */
329 u32 res; /* last read value */
330 };
331
332 struct azx {
333 struct snd_card *card;
334 struct pci_dev *pci;
335 int dev_index;
336
337 /* chip type specific */
338 int driver_type;
339 int playback_streams;
340 int playback_index_offset;
341 int capture_streams;
342 int capture_index_offset;
343 int num_streams;
344
345 /* pci resources */
346 unsigned long addr;
347 void __iomem *remap_addr;
348 int irq;
349
350 /* locks */
351 spinlock_t reg_lock;
352 struct mutex open_mutex;
353
354 /* streams (x num_streams) */
355 struct azx_dev *azx_dev;
356
357 /* PCM */
358 struct snd_pcm *pcm[AZX_MAX_PCMS];
359
360 /* HD codec */
361 unsigned short codec_mask;
362 struct hda_bus *bus;
363
364 /* CORB/RIRB */
365 struct azx_rb corb;
366 struct azx_rb rirb;
367
368 /* CORB/RIRB and position buffers */
369 struct snd_dma_buffer rb;
370 struct snd_dma_buffer posbuf;
371
372 /* flags */
373 int position_fix;
374 unsigned int running :1;
375 unsigned int initialized :1;
376 unsigned int single_cmd :1;
377 unsigned int polling_mode :1;
378 unsigned int msi :1;
379 unsigned int irq_pending_warned :1;
380
381 /* for debugging */
382 unsigned int last_cmd; /* last issued command (to sync) */
383
384 /* for pending irqs */
385 struct work_struct irq_pending_work;
386 };
387
388 /* driver types */
389 enum {
390 AZX_DRIVER_ICH,
391 AZX_DRIVER_SCH,
392 AZX_DRIVER_ATI,
393 AZX_DRIVER_ATIHDMI,
394 AZX_DRIVER_VIA,
395 AZX_DRIVER_SIS,
396 AZX_DRIVER_ULI,
397 AZX_DRIVER_NVIDIA,
398 AZX_DRIVER_TERA,
399 };
400
401 static char *driver_short_names[] __devinitdata = {
402 [AZX_DRIVER_ICH] = "HDA Intel",
403 [AZX_DRIVER_SCH] = "HDA Intel MID",
404 [AZX_DRIVER_ATI] = "HDA ATI SB",
405 [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI",
406 [AZX_DRIVER_VIA] = "HDA VIA VT82xx",
407 [AZX_DRIVER_SIS] = "HDA SIS966",
408 [AZX_DRIVER_ULI] = "HDA ULI M5461",
409 [AZX_DRIVER_NVIDIA] = "HDA NVidia",
410 [AZX_DRIVER_TERA] = "HDA Teradici",
411 };
412
413 /*
414 * macros for easy use
415 */
416 #define azx_writel(chip,reg,value) \
417 writel(value, (chip)->remap_addr + ICH6_REG_##reg)
418 #define azx_readl(chip,reg) \
419 readl((chip)->remap_addr + ICH6_REG_##reg)
420 #define azx_writew(chip,reg,value) \
421 writew(value, (chip)->remap_addr + ICH6_REG_##reg)
422 #define azx_readw(chip,reg) \
423 readw((chip)->remap_addr + ICH6_REG_##reg)
424 #define azx_writeb(chip,reg,value) \
425 writeb(value, (chip)->remap_addr + ICH6_REG_##reg)
426 #define azx_readb(chip,reg) \
427 readb((chip)->remap_addr + ICH6_REG_##reg)
428
429 #define azx_sd_writel(dev,reg,value) \
430 writel(value, (dev)->sd_addr + ICH6_REG_##reg)
431 #define azx_sd_readl(dev,reg) \
432 readl((dev)->sd_addr + ICH6_REG_##reg)
433 #define azx_sd_writew(dev,reg,value) \
434 writew(value, (dev)->sd_addr + ICH6_REG_##reg)
435 #define azx_sd_readw(dev,reg) \
436 readw((dev)->sd_addr + ICH6_REG_##reg)
437 #define azx_sd_writeb(dev,reg,value) \
438 writeb(value, (dev)->sd_addr + ICH6_REG_##reg)
439 #define azx_sd_readb(dev,reg) \
440 readb((dev)->sd_addr + ICH6_REG_##reg)
441
442 /* for pcm support */
443 #define get_azx_dev(substream) (substream->runtime->private_data)
444
445 /* Get the upper 32bit of the given dma_addr_t
446 * Compiler should optimize and eliminate the code if dma_addr_t is 32bit
447 */
448 #define upper_32bit(addr) (sizeof(addr) > 4 ? (u32)((addr) >> 32) : (u32)0)
449
450 static int azx_acquire_irq(struct azx *chip, int do_disconnect);
451
452 /*
453 * Interface for HD codec
454 */
455
456 /*
457 * CORB / RIRB interface
458 */
459 static int azx_alloc_cmd_io(struct azx *chip)
460 {
461 int err;
462
463 /* single page (at least 4096 bytes) must suffice for both ringbuffes */
464 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
465 snd_dma_pci_data(chip->pci),
466 PAGE_SIZE, &chip->rb);
467 if (err < 0) {
468 snd_printk(KERN_ERR SFX "cannot allocate CORB/RIRB\n");
469 return err;
470 }
471 return 0;
472 }
473
474 static void azx_init_cmd_io(struct azx *chip)
475 {
476 /* CORB set up */
477 chip->corb.addr = chip->rb.addr;
478 chip->corb.buf = (u32 *)chip->rb.area;
479 azx_writel(chip, CORBLBASE, (u32)chip->corb.addr);
480 azx_writel(chip, CORBUBASE, upper_32bit(chip->corb.addr));
481
482 /* set the corb size to 256 entries (ULI requires explicitly) */
483 azx_writeb(chip, CORBSIZE, 0x02);
484 /* set the corb write pointer to 0 */
485 azx_writew(chip, CORBWP, 0);
486 /* reset the corb hw read pointer */
487 azx_writew(chip, CORBRP, ICH6_RBRWP_CLR);
488 /* enable corb dma */
489 azx_writeb(chip, CORBCTL, ICH6_RBCTL_DMA_EN);
490
491 /* RIRB set up */
492 chip->rirb.addr = chip->rb.addr + 2048;
493 chip->rirb.buf = (u32 *)(chip->rb.area + 2048);
494 azx_writel(chip, RIRBLBASE, (u32)chip->rirb.addr);
495 azx_writel(chip, RIRBUBASE, upper_32bit(chip->rirb.addr));
496
497 /* set the rirb size to 256 entries (ULI requires explicitly) */
498 azx_writeb(chip, RIRBSIZE, 0x02);
499 /* reset the rirb hw write pointer */
500 azx_writew(chip, RIRBWP, ICH6_RBRWP_CLR);
501 /* set N=1, get RIRB response interrupt for new entry */
502 azx_writew(chip, RINTCNT, 1);
503 /* enable rirb dma and response irq */
504 azx_writeb(chip, RIRBCTL, ICH6_RBCTL_DMA_EN | ICH6_RBCTL_IRQ_EN);
505 chip->rirb.rp = chip->rirb.cmds = 0;
506 }
507
508 static void azx_free_cmd_io(struct azx *chip)
509 {
510 /* disable ringbuffer DMAs */
511 azx_writeb(chip, RIRBCTL, 0);
512 azx_writeb(chip, CORBCTL, 0);
513 }
514
515 /* send a command */
516 static int azx_corb_send_cmd(struct hda_codec *codec, u32 val)
517 {
518 struct azx *chip = codec->bus->private_data;
519 unsigned int wp;
520
521 /* add command to corb */
522 wp = azx_readb(chip, CORBWP);
523 wp++;
524 wp %= ICH6_MAX_CORB_ENTRIES;
525
526 spin_lock_irq(&chip->reg_lock);
527 chip->rirb.cmds++;
528 chip->corb.buf[wp] = cpu_to_le32(val);
529 azx_writel(chip, CORBWP, wp);
530 spin_unlock_irq(&chip->reg_lock);
531
532 return 0;
533 }
534
535 #define ICH6_RIRB_EX_UNSOL_EV (1<<4)
536
537 /* retrieve RIRB entry - called from interrupt handler */
538 static void azx_update_rirb(struct azx *chip)
539 {
540 unsigned int rp, wp;
541 u32 res, res_ex;
542
543 wp = azx_readb(chip, RIRBWP);
544 if (wp == chip->rirb.wp)
545 return;
546 chip->rirb.wp = wp;
547
548 while (chip->rirb.rp != wp) {
549 chip->rirb.rp++;
550 chip->rirb.rp %= ICH6_MAX_RIRB_ENTRIES;
551
552 rp = chip->rirb.rp << 1; /* an RIRB entry is 8-bytes */
553 res_ex = le32_to_cpu(chip->rirb.buf[rp + 1]);
554 res = le32_to_cpu(chip->rirb.buf[rp]);
555 if (res_ex & ICH6_RIRB_EX_UNSOL_EV)
556 snd_hda_queue_unsol_event(chip->bus, res, res_ex);
557 else if (chip->rirb.cmds) {
558 chip->rirb.res = res;
559 smp_wmb();
560 chip->rirb.cmds--;
561 }
562 }
563 }
564
565 /* receive a response */
566 static unsigned int azx_rirb_get_response(struct hda_codec *codec)
567 {
568 struct azx *chip = codec->bus->private_data;
569 unsigned long timeout;
570
571 again:
572 timeout = jiffies + msecs_to_jiffies(1000);
573 for (;;) {
574 if (chip->polling_mode) {
575 spin_lock_irq(&chip->reg_lock);
576 azx_update_rirb(chip);
577 spin_unlock_irq(&chip->reg_lock);
578 }
579 if (!chip->rirb.cmds) {
580 smp_rmb();
581 return chip->rirb.res; /* the last value */
582 }
583 if (time_after(jiffies, timeout))
584 break;
585 if (codec->bus->needs_damn_long_delay)
586 msleep(2); /* temporary workaround */
587 else {
588 udelay(10);
589 cond_resched();
590 }
591 }
592
593 if (chip->msi) {
594 snd_printk(KERN_WARNING "hda_intel: No response from codec, "
595 "disabling MSI: last cmd=0x%08x\n", chip->last_cmd);
596 free_irq(chip->irq, chip);
597 chip->irq = -1;
598 pci_disable_msi(chip->pci);
599 chip->msi = 0;
600 if (azx_acquire_irq(chip, 1) < 0)
601 return -1;
602 goto again;
603 }
604
605 if (!chip->polling_mode) {
606 snd_printk(KERN_WARNING "hda_intel: azx_get_response timeout, "
607 "switching to polling mode: last cmd=0x%08x\n",
608 chip->last_cmd);
609 chip->polling_mode = 1;
610 goto again;
611 }
612
613 snd_printk(KERN_ERR "hda_intel: azx_get_response timeout, "
614 "switching to single_cmd mode: last cmd=0x%08x\n",
615 chip->last_cmd);
616 chip->rirb.rp = azx_readb(chip, RIRBWP);
617 chip->rirb.cmds = 0;
618 /* switch to single_cmd mode */
619 chip->single_cmd = 1;
620 azx_free_cmd_io(chip);
621 return -1;
622 }
623
624 /*
625 * Use the single immediate command instead of CORB/RIRB for simplicity
626 *
627 * Note: according to Intel, this is not preferred use. The command was
628 * intended for the BIOS only, and may get confused with unsolicited
629 * responses. So, we shouldn't use it for normal operation from the
630 * driver.
631 * I left the codes, however, for debugging/testing purposes.
632 */
633
634 /* send a command */
635 static int azx_single_send_cmd(struct hda_codec *codec, u32 val)
636 {
637 struct azx *chip = codec->bus->private_data;
638 int timeout = 50;
639
640 while (timeout--) {
641 /* check ICB busy bit */
642 if (!((azx_readw(chip, IRS) & ICH6_IRS_BUSY))) {
643 /* Clear IRV valid bit */
644 azx_writew(chip, IRS, azx_readw(chip, IRS) |
645 ICH6_IRS_VALID);
646 azx_writel(chip, IC, val);
647 azx_writew(chip, IRS, azx_readw(chip, IRS) |
648 ICH6_IRS_BUSY);
649 return 0;
650 }
651 udelay(1);
652 }
653 if (printk_ratelimit())
654 snd_printd(SFX "send_cmd timeout: IRS=0x%x, val=0x%x\n",
655 azx_readw(chip, IRS), val);
656 return -EIO;
657 }
658
659 /* receive a response */
660 static unsigned int azx_single_get_response(struct hda_codec *codec)
661 {
662 struct azx *chip = codec->bus->private_data;
663 int timeout = 50;
664
665 while (timeout--) {
666 /* check IRV busy bit */
667 if (azx_readw(chip, IRS) & ICH6_IRS_VALID)
668 return azx_readl(chip, IR);
669 udelay(1);
670 }
671 if (printk_ratelimit())
672 snd_printd(SFX "get_response timeout: IRS=0x%x\n",
673 azx_readw(chip, IRS));
674 return (unsigned int)-1;
675 }
676
677 /*
678 * The below are the main callbacks from hda_codec.
679 *
680 * They are just the skeleton to call sub-callbacks according to the
681 * current setting of chip->single_cmd.
682 */
683
684 /* send a command */
685 static int azx_send_cmd(struct hda_codec *codec, hda_nid_t nid,
686 int direct, unsigned int verb,
687 unsigned int para)
688 {
689 struct azx *chip = codec->bus->private_data;
690 u32 val;
691
692 val = (u32)(codec->addr & 0x0f) << 28;
693 val |= (u32)direct << 27;
694 val |= (u32)nid << 20;
695 val |= verb << 8;
696 val |= para;
697 chip->last_cmd = val;
698
699 if (chip->single_cmd)
700 return azx_single_send_cmd(codec, val);
701 else
702 return azx_corb_send_cmd(codec, val);
703 }
704
705 /* get a response */
706 static unsigned int azx_get_response(struct hda_codec *codec)
707 {
708 struct azx *chip = codec->bus->private_data;
709 if (chip->single_cmd)
710 return azx_single_get_response(codec);
711 else
712 return azx_rirb_get_response(codec);
713 }
714
715 #ifdef CONFIG_SND_HDA_POWER_SAVE
716 static void azx_power_notify(struct hda_codec *codec);
717 #endif
718
719 /* reset codec link */
720 static int azx_reset(struct azx *chip)
721 {
722 int count;
723
724 /* clear STATESTS */
725 azx_writeb(chip, STATESTS, STATESTS_INT_MASK);
726
727 /* reset controller */
728 azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_RESET);
729
730 count = 50;
731 while (azx_readb(chip, GCTL) && --count)
732 msleep(1);
733
734 /* delay for >= 100us for codec PLL to settle per spec
735 * Rev 0.9 section 5.5.1
736 */
737 msleep(1);
738
739 /* Bring controller out of reset */
740 azx_writeb(chip, GCTL, azx_readb(chip, GCTL) | ICH6_GCTL_RESET);
741
742 count = 50;
743 while (!azx_readb(chip, GCTL) && --count)
744 msleep(1);
745
746 /* Brent Chartrand said to wait >= 540us for codecs to initialize */
747 msleep(1);
748
749 /* check to see if controller is ready */
750 if (!azx_readb(chip, GCTL)) {
751 snd_printd("azx_reset: controller not ready!\n");
752 return -EBUSY;
753 }
754
755 /* Accept unsolicited responses */
756 azx_writel(chip, GCTL, azx_readl(chip, GCTL) | ICH6_GCTL_UREN);
757
758 /* detect codecs */
759 if (!chip->codec_mask) {
760 chip->codec_mask = azx_readw(chip, STATESTS);
761 snd_printdd("codec_mask = 0x%x\n", chip->codec_mask);
762 }
763
764 return 0;
765 }
766
767
768 /*
769 * Lowlevel interface
770 */
771
772 /* enable interrupts */
773 static void azx_int_enable(struct azx *chip)
774 {
775 /* enable controller CIE and GIE */
776 azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) |
777 ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN);
778 }
779
780 /* disable interrupts */
781 static void azx_int_disable(struct azx *chip)
782 {
783 int i;
784
785 /* disable interrupts in stream descriptor */
786 for (i = 0; i < chip->num_streams; i++) {
787 struct azx_dev *azx_dev = &chip->azx_dev[i];
788 azx_sd_writeb(azx_dev, SD_CTL,
789 azx_sd_readb(azx_dev, SD_CTL) & ~SD_INT_MASK);
790 }
791
792 /* disable SIE for all streams */
793 azx_writeb(chip, INTCTL, 0);
794
795 /* disable controller CIE and GIE */
796 azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) &
797 ~(ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN));
798 }
799
800 /* clear interrupts */
801 static void azx_int_clear(struct azx *chip)
802 {
803 int i;
804
805 /* clear stream status */
806 for (i = 0; i < chip->num_streams; i++) {
807 struct azx_dev *azx_dev = &chip->azx_dev[i];
808 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
809 }
810
811 /* clear STATESTS */
812 azx_writeb(chip, STATESTS, STATESTS_INT_MASK);
813
814 /* clear rirb status */
815 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
816
817 /* clear int status */
818 azx_writel(chip, INTSTS, ICH6_INT_CTRL_EN | ICH6_INT_ALL_STREAM);
819 }
820
821 /* start a stream */
822 static void azx_stream_start(struct azx *chip, struct azx_dev *azx_dev)
823 {
824 /* enable SIE */
825 azx_writeb(chip, INTCTL,
826 azx_readb(chip, INTCTL) | (1 << azx_dev->index));
827 /* set DMA start and interrupt mask */
828 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
829 SD_CTL_DMA_START | SD_INT_MASK);
830 }
831
832 /* stop a stream */
833 static void azx_stream_stop(struct azx *chip, struct azx_dev *azx_dev)
834 {
835 /* stop DMA */
836 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) &
837 ~(SD_CTL_DMA_START | SD_INT_MASK));
838 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK); /* to be sure */
839 /* disable SIE */
840 azx_writeb(chip, INTCTL,
841 azx_readb(chip, INTCTL) & ~(1 << azx_dev->index));
842 }
843
844
845 /*
846 * reset and start the controller registers
847 */
848 static void azx_init_chip(struct azx *chip)
849 {
850 if (chip->initialized)
851 return;
852
853 /* reset controller */
854 azx_reset(chip);
855
856 /* initialize interrupts */
857 azx_int_clear(chip);
858 azx_int_enable(chip);
859
860 /* initialize the codec command I/O */
861 if (!chip->single_cmd)
862 azx_init_cmd_io(chip);
863
864 /* program the position buffer */
865 azx_writel(chip, DPLBASE, (u32)chip->posbuf.addr);
866 azx_writel(chip, DPUBASE, upper_32bit(chip->posbuf.addr));
867
868 chip->initialized = 1;
869 }
870
871 /*
872 * initialize the PCI registers
873 */
874 /* update bits in a PCI register byte */
875 static void update_pci_byte(struct pci_dev *pci, unsigned int reg,
876 unsigned char mask, unsigned char val)
877 {
878 unsigned char data;
879
880 pci_read_config_byte(pci, reg, &data);
881 data &= ~mask;
882 data |= (val & mask);
883 pci_write_config_byte(pci, reg, data);
884 }
885
886 static void azx_init_pci(struct azx *chip)
887 {
888 unsigned short snoop;
889
890 /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
891 * TCSEL == Traffic Class Select Register, which sets PCI express QOS
892 * Ensuring these bits are 0 clears playback static on some HD Audio
893 * codecs
894 */
895 update_pci_byte(chip->pci, ICH6_PCIREG_TCSEL, 0x07, 0);
896
897 switch (chip->driver_type) {
898 case AZX_DRIVER_ATI:
899 /* For ATI SB450 azalia HD audio, we need to enable snoop */
900 update_pci_byte(chip->pci,
901 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR,
902 0x07, ATI_SB450_HDAUDIO_ENABLE_SNOOP);
903 break;
904 case AZX_DRIVER_NVIDIA:
905 /* For NVIDIA HDA, enable snoop */
906 update_pci_byte(chip->pci,
907 NVIDIA_HDA_TRANSREG_ADDR,
908 0x0f, NVIDIA_HDA_ENABLE_COHBITS);
909 break;
910 case AZX_DRIVER_SCH:
911 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop);
912 if (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP) {
913 pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC, \
914 snoop & (~INTEL_SCH_HDA_DEVC_NOSNOOP));
915 pci_read_config_word(chip->pci,
916 INTEL_SCH_HDA_DEVC, &snoop);
917 snd_printdd("HDA snoop disabled, enabling ... %s\n",\
918 (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP) \
919 ? "Failed" : "OK");
920 }
921 break;
922
923 }
924 }
925
926
927 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev);
928
929 /*
930 * interrupt handler
931 */
932 static irqreturn_t azx_interrupt(int irq, void *dev_id, struct pt_regs *regs)
933 {
934 struct azx *chip = dev_id;
935 struct azx_dev *azx_dev;
936 u32 status;
937 int i;
938
939 spin_lock(&chip->reg_lock);
940
941 status = azx_readl(chip, INTSTS);
942 if (status == 0) {
943 spin_unlock(&chip->reg_lock);
944 return IRQ_NONE;
945 }
946
947 for (i = 0; i < chip->num_streams; i++) {
948 azx_dev = &chip->azx_dev[i];
949 if (status & azx_dev->sd_int_sta_mask) {
950 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
951 if (!azx_dev->substream || !azx_dev->running)
952 continue;
953 /* ignore the first dummy IRQ (due to pos_adj) */
954 if (azx_dev->irq_ignore) {
955 azx_dev->irq_ignore = 0;
956 continue;
957 }
958 /* check whether this IRQ is really acceptable */
959 if (azx_position_ok(chip, azx_dev)) {
960 azx_dev->irq_pending = 0;
961 spin_unlock(&chip->reg_lock);
962 snd_pcm_period_elapsed(azx_dev->substream);
963 spin_lock(&chip->reg_lock);
964 } else {
965 /* bogus IRQ, process it later */
966 azx_dev->irq_pending = 1;
967 schedule_work(&chip->irq_pending_work);
968 }
969 }
970 }
971
972 /* clear rirb int */
973 status = azx_readb(chip, RIRBSTS);
974 if (status & RIRB_INT_MASK) {
975 if (!chip->single_cmd && (status & RIRB_INT_RESPONSE))
976 azx_update_rirb(chip);
977 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
978 }
979
980 #if 0
981 /* clear state status int */
982 if (azx_readb(chip, STATESTS) & 0x04)
983 azx_writeb(chip, STATESTS, 0x04);
984 #endif
985 spin_unlock(&chip->reg_lock);
986
987 return IRQ_HANDLED;
988 }
989
990
991 /*
992 * set up a BDL entry
993 */
994 static int setup_bdle(struct snd_pcm_substream *substream,
995 struct azx_dev *azx_dev, u32 **bdlp,
996 int ofs, int size, int with_ioc)
997 {
998 struct snd_sg_buf *sgbuf = snd_pcm_substream_sgbuf(substream);
999 u32 *bdl = *bdlp;
1000
1001 while (size > 0) {
1002 dma_addr_t addr;
1003 int chunk;
1004
1005 if (azx_dev->frags >= AZX_MAX_BDL_ENTRIES)
1006 return -EINVAL;
1007
1008 addr = snd_pcm_sgbuf_get_addr(sgbuf, ofs);
1009 /* program the address field of the BDL entry */
1010 bdl[0] = cpu_to_le32((u32)addr);
1011 bdl[1] = cpu_to_le32(upper_32bit(addr));
1012 /* program the size field of the BDL entry */
1013 chunk = PAGE_SIZE - (ofs % PAGE_SIZE);
1014 if (size < chunk)
1015 chunk = size;
1016 bdl[2] = cpu_to_le32(chunk);
1017 /* program the IOC to enable interrupt
1018 * only when the whole fragment is processed
1019 */
1020 size -= chunk;
1021 bdl[3] = (size || !with_ioc) ? 0 : cpu_to_le32(0x01);
1022 bdl += 4;
1023 azx_dev->frags++;
1024 ofs += chunk;
1025 }
1026 *bdlp = bdl;
1027 return ofs;
1028 }
1029
1030 /*
1031 * set up BDL entries
1032 */
1033 static int azx_setup_periods(struct azx *chip,
1034 struct snd_pcm_substream *substream,
1035 struct azx_dev *azx_dev)
1036 {
1037 u32 *bdl;
1038 int i, ofs, periods, period_bytes;
1039 int pos_adj;
1040
1041 /* reset BDL address */
1042 azx_sd_writel(azx_dev, SD_BDLPL, 0);
1043 azx_sd_writel(azx_dev, SD_BDLPU, 0);
1044
1045 period_bytes = snd_pcm_lib_period_bytes(substream);
1046 azx_dev->period_bytes = period_bytes;
1047 periods = azx_dev->bufsize / period_bytes;
1048
1049 /* program the initial BDL entries */
1050 bdl = (u32 *)azx_dev->bdl.area;
1051 ofs = 0;
1052 azx_dev->frags = 0;
1053 azx_dev->irq_ignore = 0;
1054 pos_adj = bdl_pos_adj[chip->dev_index];
1055 if (pos_adj > 0) {
1056 struct snd_pcm_runtime *runtime = substream->runtime;
1057 int pos_align = pos_adj;
1058 pos_adj = (pos_adj * runtime->rate + 47999) / 48000;
1059 if (!pos_adj)
1060 pos_adj = pos_align;
1061 else
1062 pos_adj = ((pos_adj + pos_align - 1) / pos_align) *
1063 pos_align;
1064 pos_adj = frames_to_bytes(runtime, pos_adj);
1065 if (pos_adj >= period_bytes) {
1066 snd_printk(KERN_WARNING "Too big adjustment %d\n",
1067 bdl_pos_adj[chip->dev_index]);
1068 pos_adj = 0;
1069 } else {
1070 ofs = setup_bdle(substream, azx_dev,
1071 &bdl, ofs, pos_adj, 1);
1072 if (ofs < 0)
1073 goto error;
1074 azx_dev->irq_ignore = 1;
1075 }
1076 } else
1077 pos_adj = 0;
1078 for (i = 0; i < periods; i++) {
1079 if (i == periods - 1 && pos_adj)
1080 ofs = setup_bdle(substream, azx_dev, &bdl, ofs,
1081 period_bytes - pos_adj, 0);
1082 else
1083 ofs = setup_bdle(substream, azx_dev, &bdl, ofs,
1084 period_bytes, 1);
1085 if (ofs < 0)
1086 goto error;
1087 }
1088 return 0;
1089
1090 error:
1091 snd_printk(KERN_ERR "Too many BDL entries: buffer=%d, period=%d\n",
1092 azx_dev->bufsize, period_bytes);
1093 /* reset */
1094 azx_sd_writel(azx_dev, SD_BDLPL, 0);
1095 azx_sd_writel(azx_dev, SD_BDLPU, 0);
1096 return -EINVAL;
1097 }
1098
1099 /*
1100 * set up the SD for streaming
1101 */
1102 static int azx_setup_controller(struct azx *chip, struct azx_dev *azx_dev)
1103 {
1104 unsigned char val;
1105 int timeout;
1106
1107 /* make sure the run bit is zero for SD */
1108 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) &
1109 ~SD_CTL_DMA_START);
1110 /* reset stream */
1111 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
1112 SD_CTL_STREAM_RESET);
1113 udelay(3);
1114 timeout = 300;
1115 while (!((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
1116 --timeout)
1117 ;
1118 val &= ~SD_CTL_STREAM_RESET;
1119 azx_sd_writeb(azx_dev, SD_CTL, val);
1120 udelay(3);
1121
1122 timeout = 300;
1123 /* waiting for hardware to report that the stream is out of reset */
1124 while (((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
1125 --timeout)
1126 ;
1127
1128 /* program the stream_tag */
1129 azx_sd_writel(azx_dev, SD_CTL,
1130 (azx_sd_readl(azx_dev, SD_CTL) & ~SD_CTL_STREAM_TAG_MASK)|
1131 (azx_dev->stream_tag << SD_CTL_STREAM_TAG_SHIFT));
1132
1133 /* program the length of samples in cyclic buffer */
1134 azx_sd_writel(azx_dev, SD_CBL, azx_dev->bufsize);
1135
1136 /* program the stream format */
1137 /* this value needs to be the same as the one programmed */
1138 azx_sd_writew(azx_dev, SD_FORMAT, azx_dev->format_val);
1139
1140 /* program the stream LVI (last valid index) of the BDL */
1141 azx_sd_writew(azx_dev, SD_LVI, azx_dev->frags - 1);
1142
1143 /* program the BDL address */
1144 /* lower BDL address */
1145 azx_sd_writel(azx_dev, SD_BDLPL, (u32)azx_dev->bdl.addr);
1146 /* upper BDL address */
1147 azx_sd_writel(azx_dev, SD_BDLPU, upper_32bit(azx_dev->bdl.addr));
1148
1149 /* enable the position buffer */
1150 if (chip->position_fix == POS_FIX_POSBUF ||
1151 chip->position_fix == POS_FIX_AUTO) {
1152 if (!(azx_readl(chip, DPLBASE) & ICH6_DPLBASE_ENABLE))
1153 azx_writel(chip, DPLBASE,
1154 (u32)chip->posbuf.addr | ICH6_DPLBASE_ENABLE);
1155 }
1156
1157 /* set the interrupt enable bits in the descriptor control register */
1158 azx_sd_writel(azx_dev, SD_CTL,
1159 azx_sd_readl(azx_dev, SD_CTL) | SD_INT_MASK);
1160
1161 return 0;
1162 }
1163
1164
1165 /*
1166 * Codec initialization
1167 */
1168
1169 static unsigned int azx_max_codecs[] __devinitdata = {
1170 [AZX_DRIVER_ICH] = 4, /* Some ICH9 boards use SD3 */
1171 [AZX_DRIVER_SCH] = 3,
1172 [AZX_DRIVER_ATI] = 4,
1173 [AZX_DRIVER_ATIHDMI] = 4,
1174 [AZX_DRIVER_VIA] = 3, /* FIXME: correct? */
1175 [AZX_DRIVER_SIS] = 3, /* FIXME: correct? */
1176 [AZX_DRIVER_ULI] = 3, /* FIXME: correct? */
1177 [AZX_DRIVER_NVIDIA] = 3, /* FIXME: correct? */
1178 [AZX_DRIVER_TERA] = 1,
1179 };
1180
1181 static int __devinit azx_codec_create(struct azx *chip, const char *model,
1182 unsigned int codec_probe_mask)
1183 {
1184 struct hda_bus_template bus_temp;
1185 int c, codecs, audio_codecs, err;
1186
1187 memset(&bus_temp, 0, sizeof(bus_temp));
1188 bus_temp.private_data = chip;
1189 bus_temp.modelname = model;
1190 bus_temp.pci = chip->pci;
1191 bus_temp.ops.command = azx_send_cmd;
1192 bus_temp.ops.get_response = azx_get_response;
1193 #ifdef CONFIG_SND_HDA_POWER_SAVE
1194 bus_temp.ops.pm_notify = azx_power_notify;
1195 #endif
1196
1197 err = snd_hda_bus_new(chip->card, &bus_temp, &chip->bus);
1198 if (err < 0)
1199 return err;
1200
1201 codecs = audio_codecs = 0;
1202 for (c = 0; c < AZX_MAX_CODECS; c++) {
1203 if ((chip->codec_mask & (1 << c)) & codec_probe_mask) {
1204 struct hda_codec *codec;
1205 err = snd_hda_codec_new(chip->bus, c, &codec);
1206 if (err < 0)
1207 continue;
1208 codecs++;
1209 if (codec->afg)
1210 audio_codecs++;
1211 }
1212 }
1213 if (!audio_codecs) {
1214 /* probe additional slots if no codec is found */
1215 for (; c < azx_max_codecs[chip->driver_type]; c++) {
1216 if ((chip->codec_mask & (1 << c)) & codec_probe_mask) {
1217 err = snd_hda_codec_new(chip->bus, c, NULL);
1218 if (err < 0)
1219 continue;
1220 codecs++;
1221 }
1222 }
1223 }
1224 if (!codecs) {
1225 snd_printk(KERN_ERR SFX "no codecs initialized\n");
1226 return -ENXIO;
1227 }
1228
1229 return 0;
1230 }
1231
1232
1233 /*
1234 * PCM support
1235 */
1236
1237 /* assign a stream for the PCM */
1238 static inline struct azx_dev *azx_assign_device(struct azx *chip, int stream)
1239 {
1240 int dev, i, nums;
1241 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
1242 dev = chip->playback_index_offset;
1243 nums = chip->playback_streams;
1244 } else {
1245 dev = chip->capture_index_offset;
1246 nums = chip->capture_streams;
1247 }
1248 for (i = 0; i < nums; i++, dev++)
1249 if (!chip->azx_dev[dev].opened) {
1250 chip->azx_dev[dev].opened = 1;
1251 return &chip->azx_dev[dev];
1252 }
1253 return NULL;
1254 }
1255
1256 /* release the assigned stream */
1257 static inline void azx_release_device(struct azx_dev *azx_dev)
1258 {
1259 azx_dev->opened = 0;
1260 }
1261
1262 static struct snd_pcm_hardware azx_pcm_hw = {
1263 .info = (SNDRV_PCM_INFO_MMAP |
1264 SNDRV_PCM_INFO_INTERLEAVED |
1265 SNDRV_PCM_INFO_BLOCK_TRANSFER |
1266 SNDRV_PCM_INFO_MMAP_VALID |
1267 /* No full-resume yet implemented */
1268 /* SNDRV_PCM_INFO_RESUME |*/
1269 SNDRV_PCM_INFO_PAUSE |
1270 SNDRV_PCM_INFO_SYNC_START),
1271 .formats = SNDRV_PCM_FMTBIT_S16_LE,
1272 .rates = SNDRV_PCM_RATE_48000,
1273 .rate_min = 48000,
1274 .rate_max = 48000,
1275 .channels_min = 2,
1276 .channels_max = 2,
1277 .buffer_bytes_max = AZX_MAX_BUF_SIZE,
1278 .period_bytes_min = 128,
1279 .period_bytes_max = AZX_MAX_BUF_SIZE / 2,
1280 .periods_min = 2,
1281 .periods_max = AZX_MAX_FRAG,
1282 .fifo_size = 0,
1283 };
1284
1285 struct azx_pcm {
1286 struct azx *chip;
1287 struct hda_codec *codec;
1288 struct hda_pcm_stream *hinfo[2];
1289 };
1290
1291 static int azx_pcm_open(struct snd_pcm_substream *substream)
1292 {
1293 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1294 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1295 struct azx *chip = apcm->chip;
1296 struct azx_dev *azx_dev;
1297 struct snd_pcm_runtime *runtime = substream->runtime;
1298 unsigned long flags;
1299 int err;
1300
1301 mutex_lock(&chip->open_mutex);
1302 azx_dev = azx_assign_device(chip, substream->stream);
1303 if (azx_dev == NULL) {
1304 mutex_unlock(&chip->open_mutex);
1305 return -EBUSY;
1306 }
1307 runtime->hw = azx_pcm_hw;
1308 runtime->hw.channels_min = hinfo->channels_min;
1309 runtime->hw.channels_max = hinfo->channels_max;
1310 runtime->hw.formats = hinfo->formats;
1311 runtime->hw.rates = hinfo->rates;
1312 snd_pcm_limit_hw_rates(runtime);
1313 snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS);
1314 snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
1315 128);
1316 snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
1317 128);
1318 snd_hda_power_up(apcm->codec);
1319 err = hinfo->ops.open(hinfo, apcm->codec, substream);
1320 if (err < 0) {
1321 azx_release_device(azx_dev);
1322 snd_hda_power_down(apcm->codec);
1323 mutex_unlock(&chip->open_mutex);
1324 return err;
1325 }
1326 spin_lock_irqsave(&chip->reg_lock, flags);
1327 azx_dev->substream = substream;
1328 azx_dev->running = 0;
1329 spin_unlock_irqrestore(&chip->reg_lock, flags);
1330
1331 runtime->private_data = azx_dev;
1332 snd_pcm_set_sync(substream);
1333 mutex_unlock(&chip->open_mutex);
1334 return 0;
1335 }
1336
1337 static int azx_pcm_close(struct snd_pcm_substream *substream)
1338 {
1339 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1340 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1341 struct azx *chip = apcm->chip;
1342 struct azx_dev *azx_dev = get_azx_dev(substream);
1343 unsigned long flags;
1344
1345 mutex_lock(&chip->open_mutex);
1346 spin_lock_irqsave(&chip->reg_lock, flags);
1347 azx_dev->substream = NULL;
1348 azx_dev->running = 0;
1349 spin_unlock_irqrestore(&chip->reg_lock, flags);
1350 azx_release_device(azx_dev);
1351 hinfo->ops.close(hinfo, apcm->codec, substream);
1352 snd_hda_power_down(apcm->codec);
1353 mutex_unlock(&chip->open_mutex);
1354 return 0;
1355 }
1356
1357 static int azx_pcm_hw_params(struct snd_pcm_substream *substream,
1358 struct snd_pcm_hw_params *hw_params)
1359 {
1360 return snd_pcm_lib_malloc_pages(substream,
1361 params_buffer_bytes(hw_params));
1362 }
1363
1364 static int azx_pcm_hw_free(struct snd_pcm_substream *substream)
1365 {
1366 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1367 struct azx_dev *azx_dev = get_azx_dev(substream);
1368 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1369
1370 /* reset BDL address */
1371 azx_sd_writel(azx_dev, SD_BDLPL, 0);
1372 azx_sd_writel(azx_dev, SD_BDLPU, 0);
1373 azx_sd_writel(azx_dev, SD_CTL, 0);
1374
1375 hinfo->ops.cleanup(hinfo, apcm->codec, substream);
1376
1377 return snd_pcm_lib_free_pages(substream);
1378 }
1379
1380 static int azx_pcm_prepare(struct snd_pcm_substream *substream)
1381 {
1382 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1383 struct azx *chip = apcm->chip;
1384 struct azx_dev *azx_dev = get_azx_dev(substream);
1385 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1386 struct snd_pcm_runtime *runtime = substream->runtime;
1387
1388 azx_dev->bufsize = snd_pcm_lib_buffer_bytes(substream);
1389 azx_dev->format_val = snd_hda_calc_stream_format(runtime->rate,
1390 runtime->channels,
1391 runtime->format,
1392 hinfo->maxbps);
1393 if (!azx_dev->format_val) {
1394 snd_printk(KERN_ERR SFX
1395 "invalid format_val, rate=%d, ch=%d, format=%d\n",
1396 runtime->rate, runtime->channels, runtime->format);
1397 return -EINVAL;
1398 }
1399
1400 snd_printdd("azx_pcm_prepare: bufsize=0x%x, format=0x%x\n",
1401 azx_dev->bufsize, azx_dev->format_val);
1402 if (azx_setup_periods(chip, substream, azx_dev) < 0)
1403 return -EINVAL;
1404 azx_setup_controller(chip, azx_dev);
1405 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1406 azx_dev->fifo_size = azx_sd_readw(azx_dev, SD_FIFOSIZE) + 1;
1407 else
1408 azx_dev->fifo_size = 0;
1409
1410 return hinfo->ops.prepare(hinfo, apcm->codec, azx_dev->stream_tag,
1411 azx_dev->format_val, substream);
1412 }
1413
1414 static int azx_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
1415 {
1416 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1417 struct azx *chip = apcm->chip;
1418 struct azx_dev *azx_dev;
1419 struct snd_pcm_substream *s;
1420 int start, nsync = 0, sbits = 0;
1421 int nwait, timeout;
1422
1423 switch (cmd) {
1424 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1425 case SNDRV_PCM_TRIGGER_RESUME:
1426 case SNDRV_PCM_TRIGGER_START:
1427 start = 1;
1428 break;
1429 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1430 case SNDRV_PCM_TRIGGER_SUSPEND:
1431 case SNDRV_PCM_TRIGGER_STOP:
1432 start = 0;
1433 break;
1434 default:
1435 return -EINVAL;
1436 }
1437
1438 snd_pcm_group_for_each_entry(s, substream) {
1439 if (s->pcm->card != substream->pcm->card)
1440 continue;
1441 azx_dev = get_azx_dev(s);
1442 sbits |= 1 << azx_dev->index;
1443 nsync++;
1444 snd_pcm_trigger_done(s, substream);
1445 }
1446
1447 spin_lock(&chip->reg_lock);
1448 if (nsync > 1) {
1449 /* first, set SYNC bits of corresponding streams */
1450 azx_writel(chip, SYNC, azx_readl(chip, SYNC) | sbits);
1451 }
1452 snd_pcm_group_for_each_entry(s, substream) {
1453 if (s->pcm->card != substream->pcm->card)
1454 continue;
1455 azx_dev = get_azx_dev(s);
1456 if (start)
1457 azx_stream_start(chip, azx_dev);
1458 else
1459 azx_stream_stop(chip, azx_dev);
1460 azx_dev->running = start;
1461 }
1462 spin_unlock(&chip->reg_lock);
1463 if (start) {
1464 if (nsync == 1)
1465 return 0;
1466 /* wait until all FIFOs get ready */
1467 for (timeout = 5000; timeout; timeout--) {
1468 nwait = 0;
1469 snd_pcm_group_for_each_entry(s, substream) {
1470 if (s->pcm->card != substream->pcm->card)
1471 continue;
1472 azx_dev = get_azx_dev(s);
1473 if (!(azx_sd_readb(azx_dev, SD_STS) &
1474 SD_STS_FIFO_READY))
1475 nwait++;
1476 }
1477 if (!nwait)
1478 break;
1479 cpu_relax();
1480 }
1481 } else {
1482 /* wait until all RUN bits are cleared */
1483 for (timeout = 5000; timeout; timeout--) {
1484 nwait = 0;
1485 snd_pcm_group_for_each_entry(s, substream) {
1486 if (s->pcm->card != substream->pcm->card)
1487 continue;
1488 azx_dev = get_azx_dev(s);
1489 if (azx_sd_readb(azx_dev, SD_CTL) &
1490 SD_CTL_DMA_START)
1491 nwait++;
1492 }
1493 if (!nwait)
1494 break;
1495 cpu_relax();
1496 }
1497 }
1498 if (nsync > 1) {
1499 spin_lock(&chip->reg_lock);
1500 /* reset SYNC bits */
1501 azx_writel(chip, SYNC, azx_readl(chip, SYNC) & ~sbits);
1502 spin_unlock(&chip->reg_lock);
1503 }
1504 return 0;
1505 }
1506
1507 static unsigned int azx_get_position(struct azx *chip,
1508 struct azx_dev *azx_dev)
1509 {
1510 unsigned int pos;
1511
1512 if (chip->position_fix == POS_FIX_POSBUF ||
1513 chip->position_fix == POS_FIX_AUTO) {
1514 /* use the position buffer */
1515 pos = le32_to_cpu(*azx_dev->posbuf);
1516 } else {
1517 /* read LPIB */
1518 pos = azx_sd_readl(azx_dev, SD_LPIB);
1519 }
1520 if (pos >= azx_dev->bufsize)
1521 pos = 0;
1522 return pos;
1523 }
1524
1525 static snd_pcm_uframes_t azx_pcm_pointer(struct snd_pcm_substream *substream)
1526 {
1527 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1528 struct azx *chip = apcm->chip;
1529 struct azx_dev *azx_dev = get_azx_dev(substream);
1530 return bytes_to_frames(substream->runtime,
1531 azx_get_position(chip, azx_dev));
1532 }
1533
1534 /*
1535 * Check whether the current DMA position is acceptable for updating
1536 * periods. Returns non-zero if it's OK.
1537 *
1538 * Many HD-audio controllers appear pretty inaccurate about
1539 * the update-IRQ timing. The IRQ is issued before actually the
1540 * data is processed. So, we need to process it afterwords in a
1541 * workqueue.
1542 */
1543 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev)
1544 {
1545 unsigned int pos;
1546
1547 pos = azx_get_position(chip, azx_dev);
1548 if (chip->position_fix == POS_FIX_AUTO) {
1549 if (!pos) {
1550 printk(KERN_WARNING
1551 "hda-intel: Invalid position buffer, "
1552 "using LPIB read method instead.\n");
1553 chip->position_fix = POS_FIX_LPIB;
1554 pos = azx_get_position(chip, azx_dev);
1555 } else
1556 chip->position_fix = POS_FIX_POSBUF;
1557 }
1558
1559 if (pos % azx_dev->period_bytes > azx_dev->period_bytes / 2)
1560 return 0; /* NG - it's below the period boundary */
1561 return 1; /* OK, it's fine */
1562 }
1563
1564 /*
1565 * The work for pending PCM period updates.
1566 */
1567 static void azx_irq_pending_work(void *data)
1568 {
1569 struct work_struct *work = data;
1570 struct azx *chip = container_of(work, struct azx, irq_pending_work);
1571 int i, pending;
1572
1573 if (!chip->irq_pending_warned) {
1574 printk(KERN_WARNING
1575 "hda-intel: IRQ timing workaround is activated "
1576 "for card #%d. Suggest a bigger bdl_pos_adj.\n",
1577 chip->card->number);
1578 chip->irq_pending_warned = 1;
1579 }
1580
1581 for (;;) {
1582 pending = 0;
1583 spin_lock_irq(&chip->reg_lock);
1584 for (i = 0; i < chip->num_streams; i++) {
1585 struct azx_dev *azx_dev = &chip->azx_dev[i];
1586 if (!azx_dev->irq_pending ||
1587 !azx_dev->substream ||
1588 !azx_dev->running)
1589 continue;
1590 if (azx_position_ok(chip, azx_dev)) {
1591 azx_dev->irq_pending = 0;
1592 spin_unlock(&chip->reg_lock);
1593 snd_pcm_period_elapsed(azx_dev->substream);
1594 spin_lock(&chip->reg_lock);
1595 } else
1596 pending++;
1597 }
1598 spin_unlock_irq(&chip->reg_lock);
1599 if (!pending)
1600 return;
1601 cond_resched();
1602 }
1603 }
1604
1605 /* clear irq_pending flags and assure no on-going workq */
1606 static void azx_clear_irq_pending(struct azx *chip)
1607 {
1608 int i;
1609
1610 spin_lock_irq(&chip->reg_lock);
1611 for (i = 0; i < chip->num_streams; i++)
1612 chip->azx_dev[i].irq_pending = 0;
1613 spin_unlock_irq(&chip->reg_lock);
1614 flush_scheduled_work();
1615 }
1616
1617 static struct snd_pcm_ops azx_pcm_ops = {
1618 .open = azx_pcm_open,
1619 .close = azx_pcm_close,
1620 .ioctl = snd_pcm_lib_ioctl,
1621 .hw_params = azx_pcm_hw_params,
1622 .hw_free = azx_pcm_hw_free,
1623 .prepare = azx_pcm_prepare,
1624 .trigger = azx_pcm_trigger,
1625 .pointer = azx_pcm_pointer,
1626 .page = snd_pcm_sgbuf_ops_page,
1627 };
1628
1629 static void azx_pcm_free(struct snd_pcm *pcm)
1630 {
1631 kfree(pcm->private_data);
1632 }
1633
1634 static int __devinit create_codec_pcm(struct azx *chip, struct hda_codec *codec,
1635 struct hda_pcm *cpcm)
1636 {
1637 int err;
1638 struct snd_pcm *pcm;
1639 struct azx_pcm *apcm;
1640
1641 /* if no substreams are defined for both playback and capture,
1642 * it's just a placeholder. ignore it.
1643 */
1644 if (!cpcm->stream[0].substreams && !cpcm->stream[1].substreams)
1645 return 0;
1646
1647 snd_assert(cpcm->name, return -EINVAL);
1648
1649 err = snd_pcm_new(chip->card, cpcm->name, cpcm->device,
1650 cpcm->stream[0].substreams,
1651 cpcm->stream[1].substreams,
1652 &pcm);
1653 if (err < 0)
1654 return err;
1655 strcpy(pcm->name, cpcm->name);
1656 apcm = kmalloc(sizeof(*apcm), GFP_KERNEL);
1657 if (apcm == NULL)
1658 return -ENOMEM;
1659 apcm->chip = chip;
1660 apcm->codec = codec;
1661 apcm->hinfo[0] = &cpcm->stream[0];
1662 apcm->hinfo[1] = &cpcm->stream[1];
1663 pcm->private_data = apcm;
1664 pcm->private_free = azx_pcm_free;
1665 if (cpcm->stream[0].substreams)
1666 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &azx_pcm_ops);
1667 if (cpcm->stream[1].substreams)
1668 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &azx_pcm_ops);
1669 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV_SG,
1670 snd_dma_pci_data(chip->pci),
1671 1024 * 64, 1024 * 1024);
1672 chip->pcm[cpcm->device] = pcm;
1673 return 0;
1674 }
1675
1676 static int __devinit azx_pcm_create(struct azx *chip)
1677 {
1678 static const char *dev_name[HDA_PCM_NTYPES] = {
1679 "Audio", "SPDIF", "HDMI", "Modem"
1680 };
1681 /* starting device index for each PCM type */
1682 static int dev_idx[HDA_PCM_NTYPES] = {
1683 [HDA_PCM_TYPE_AUDIO] = 0,
1684 [HDA_PCM_TYPE_SPDIF] = 1,
1685 [HDA_PCM_TYPE_HDMI] = 3,
1686 [HDA_PCM_TYPE_MODEM] = 6
1687 };
1688 /* normal audio device indices; not linear to keep compatibility */
1689 static int audio_idx[4] = { 0, 2, 4, 5 };
1690 struct hda_codec *codec;
1691 int c, err;
1692 int num_devs[HDA_PCM_NTYPES];
1693
1694 err = snd_hda_build_pcms(chip->bus);
1695 if (err < 0)
1696 return err;
1697
1698 /* create audio PCMs */
1699 memset(num_devs, 0, sizeof(num_devs));
1700 list_for_each_entry(codec, &chip->bus->codec_list, list) {
1701 for (c = 0; c < codec->num_pcms; c++) {
1702 struct hda_pcm *cpcm = &codec->pcm_info[c];
1703 int type = cpcm->pcm_type;
1704 switch (type) {
1705 case HDA_PCM_TYPE_AUDIO:
1706 if (num_devs[type] >= ARRAY_SIZE(audio_idx)) {
1707 snd_printk(KERN_WARNING
1708 "Too many audio devices\n");
1709 continue;
1710 }
1711 cpcm->device = audio_idx[num_devs[type]];
1712 break;
1713 case HDA_PCM_TYPE_SPDIF:
1714 case HDA_PCM_TYPE_HDMI:
1715 case HDA_PCM_TYPE_MODEM:
1716 if (num_devs[type]) {
1717 snd_printk(KERN_WARNING
1718 "%s already defined\n",
1719 dev_name[type]);
1720 continue;
1721 }
1722 cpcm->device = dev_idx[type];
1723 break;
1724 default:
1725 snd_printk(KERN_WARNING
1726 "Invalid PCM type %d\n", type);
1727 continue;
1728 }
1729 num_devs[type]++;
1730 err = create_codec_pcm(chip, codec, cpcm);
1731 if (err < 0)
1732 return err;
1733 }
1734 }
1735 return 0;
1736 }
1737
1738 /*
1739 * mixer creation - all stuff is implemented in hda module
1740 */
1741 static int __devinit azx_mixer_create(struct azx *chip)
1742 {
1743 return snd_hda_build_controls(chip->bus);
1744 }
1745
1746
1747 /*
1748 * initialize SD streams
1749 */
1750 static int __devinit azx_init_stream(struct azx *chip)
1751 {
1752 int i;
1753
1754 /* initialize each stream (aka device)
1755 * assign the starting bdl address to each stream (device)
1756 * and initialize
1757 */
1758 for (i = 0; i < chip->num_streams; i++) {
1759 struct azx_dev *azx_dev = &chip->azx_dev[i];
1760 azx_dev->posbuf = (u32 __iomem *)(chip->posbuf.area + i * 8);
1761 /* offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
1762 azx_dev->sd_addr = chip->remap_addr + (0x20 * i + 0x80);
1763 /* int mask: SDI0=0x01, SDI1=0x02, ... SDO3=0x80 */
1764 azx_dev->sd_int_sta_mask = 1 << i;
1765 /* stream tag: must be non-zero and unique */
1766 azx_dev->index = i;
1767 azx_dev->stream_tag = i + 1;
1768 }
1769
1770 return 0;
1771 }
1772
1773 static int azx_acquire_irq(struct azx *chip, int do_disconnect)
1774 {
1775 if (request_irq(chip->pci->irq, azx_interrupt,
1776 chip->msi ? 0 : IRQF_SHARED,
1777 "HDA Intel", chip)) {
1778 printk(KERN_ERR "hda-intel: unable to grab IRQ %d, "
1779 "disabling device\n", chip->pci->irq);
1780 if (do_disconnect)
1781 snd_card_disconnect(chip->card);
1782 return -1;
1783 }
1784 chip->irq = chip->pci->irq;
1785 pci_intx(chip->pci, !chip->msi);
1786 return 0;
1787 }
1788
1789
1790 static void azx_stop_chip(struct azx *chip)
1791 {
1792 if (!chip->initialized)
1793 return;
1794
1795 /* disable interrupts */
1796 azx_int_disable(chip);
1797 azx_int_clear(chip);
1798
1799 /* disable CORB/RIRB */
1800 azx_free_cmd_io(chip);
1801
1802 /* disable position buffer */
1803 azx_writel(chip, DPLBASE, 0);
1804 azx_writel(chip, DPUBASE, 0);
1805
1806 chip->initialized = 0;
1807 }
1808
1809 #ifdef CONFIG_SND_HDA_POWER_SAVE
1810 /* power-up/down the controller */
1811 static void azx_power_notify(struct hda_codec *codec)
1812 {
1813 struct azx *chip = codec->bus->private_data;
1814 struct hda_codec *c;
1815 int power_on = 0;
1816
1817 list_for_each_entry(c, &codec->bus->codec_list, list) {
1818 if (c->power_on) {
1819 power_on = 1;
1820 break;
1821 }
1822 }
1823 if (power_on)
1824 azx_init_chip(chip);
1825 else if (chip->running && power_save_controller)
1826 azx_stop_chip(chip);
1827 }
1828 #endif /* CONFIG_SND_HDA_POWER_SAVE */
1829
1830 #ifdef CONFIG_PM
1831 /*
1832 * power management
1833 */
1834 static int azx_suspend(struct pci_dev *pci, pm_message_t state)
1835 {
1836 struct snd_card *card = pci_get_drvdata(pci);
1837 struct azx *chip = card->private_data;
1838 int i;
1839
1840 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
1841 azx_clear_irq_pending(chip);
1842 for (i = 0; i < AZX_MAX_PCMS; i++)
1843 snd_pcm_suspend_all(chip->pcm[i]);
1844 if (chip->initialized)
1845 snd_hda_suspend(chip->bus, state);
1846 azx_stop_chip(chip);
1847 if (chip->irq >= 0) {
1848 free_irq(chip->irq, chip);
1849 chip->irq = -1;
1850 }
1851 if (chip->msi)
1852 pci_disable_msi(chip->pci);
1853 pci_disable_device(pci);
1854 pci_save_state(pci);
1855 pci_set_power_state(pci, pci_choose_state(pci, state));
1856 return 0;
1857 }
1858
1859 static int azx_resume(struct pci_dev *pci)
1860 {
1861 struct snd_card *card = pci_get_drvdata(pci);
1862 struct azx *chip = card->private_data;
1863
1864 pci_set_power_state(pci, PCI_D0);
1865 pci_restore_state(pci);
1866 if (pci_enable_device(pci) < 0) {
1867 printk(KERN_ERR "hda-intel: pci_enable_device failed, "
1868 "disabling device\n");
1869 snd_card_disconnect(card);
1870 return -EIO;
1871 }
1872 pci_set_master(pci);
1873 if (chip->msi)
1874 if (pci_enable_msi(pci) < 0)
1875 chip->msi = 0;
1876 if (azx_acquire_irq(chip, 1) < 0)
1877 return -EIO;
1878 azx_init_pci(chip);
1879
1880 if (snd_hda_codecs_inuse(chip->bus))
1881 azx_init_chip(chip);
1882
1883 snd_hda_resume(chip->bus);
1884 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
1885 return 0;
1886 }
1887 #endif /* CONFIG_PM */
1888
1889
1890 /*
1891 * destructor
1892 */
1893 static int azx_free(struct azx *chip)
1894 {
1895 int i;
1896
1897 if (chip->initialized) {
1898 azx_clear_irq_pending(chip);
1899 for (i = 0; i < chip->num_streams; i++)
1900 azx_stream_stop(chip, &chip->azx_dev[i]);
1901 azx_stop_chip(chip);
1902 }
1903
1904 if (chip->irq >= 0)
1905 free_irq(chip->irq, (void*)chip);
1906 if (chip->msi)
1907 pci_disable_msi(chip->pci);
1908 if (chip->remap_addr)
1909 iounmap(chip->remap_addr);
1910
1911 if (chip->azx_dev) {
1912 for (i = 0; i < chip->num_streams; i++)
1913 if (chip->azx_dev[i].bdl.area)
1914 snd_dma_free_pages(&chip->azx_dev[i].bdl);
1915 }
1916 if (chip->rb.area)
1917 snd_dma_free_pages(&chip->rb);
1918 if (chip->posbuf.area)
1919 snd_dma_free_pages(&chip->posbuf);
1920 pci_release_regions(chip->pci);
1921 pci_disable_device(chip->pci);
1922 kfree(chip->azx_dev);
1923 kfree(chip);
1924
1925 return 0;
1926 }
1927
1928 static int azx_dev_free(struct snd_device *device)
1929 {
1930 return azx_free(device->device_data);
1931 }
1932
1933 /*
1934 * white/black-listing for position_fix
1935 */
1936 static struct snd_pci_quirk position_fix_list[] __devinitdata = {
1937 SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB),
1938 SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB),
1939 SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB),
1940 {}
1941 };
1942
1943 static int __devinit check_position_fix(struct azx *chip, int fix)
1944 {
1945 const struct snd_pci_quirk *q;
1946
1947 if (fix == POS_FIX_AUTO) {
1948 q = snd_pci_quirk_lookup(chip->pci, position_fix_list);
1949 if (q) {
1950 printk(KERN_INFO
1951 "hda_intel: position_fix set to %d "
1952 "for device %04x:%04x\n",
1953 q->value, q->subvendor, q->subdevice);
1954 return q->value;
1955 }
1956 }
1957 return fix;
1958 }
1959
1960 /*
1961 * black-lists for probe_mask
1962 */
1963 static struct snd_pci_quirk probe_mask_list[] __devinitdata = {
1964 /* Thinkpad often breaks the controller communication when accessing
1965 * to the non-working (or non-existing) modem codec slot.
1966 */
1967 SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01),
1968 SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01),
1969 SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01),
1970 {}
1971 };
1972
1973 static void __devinit check_probe_mask(struct azx *chip, int dev)
1974 {
1975 const struct snd_pci_quirk *q;
1976
1977 if (probe_mask[dev] == -1) {
1978 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list);
1979 if (q) {
1980 printk(KERN_INFO
1981 "hda_intel: probe_mask set to 0x%x "
1982 "for device %04x:%04x\n",
1983 q->value, q->subvendor, q->subdevice);
1984 probe_mask[dev] = q->value;
1985 }
1986 }
1987 }
1988
1989
1990 /*
1991 * constructor
1992 */
1993 static int __devinit azx_create(struct snd_card *card, struct pci_dev *pci,
1994 int dev, int driver_type,
1995 struct azx **rchip)
1996 {
1997 struct azx *chip;
1998 int i, err;
1999 unsigned short gcap;
2000 static struct snd_device_ops ops = {
2001 .dev_free = azx_dev_free,
2002 };
2003
2004 *rchip = NULL;
2005
2006 err = pci_enable_device(pci);
2007 if (err < 0)
2008 return err;
2009
2010 chip = kzalloc(sizeof(*chip), GFP_KERNEL);
2011 if (!chip) {
2012 snd_printk(KERN_ERR SFX "cannot allocate chip\n");
2013 pci_disable_device(pci);
2014 return -ENOMEM;
2015 }
2016
2017 spin_lock_init(&chip->reg_lock);
2018 mutex_init(&chip->open_mutex);
2019 chip->card = card;
2020 chip->pci = pci;
2021 chip->irq = -1;
2022 chip->driver_type = driver_type;
2023 chip->msi = enable_msi;
2024 chip->dev_index = dev;
2025 INIT_WORK(&chip->irq_pending_work, azx_irq_pending_work, &chip->irq_pending_work);
2026
2027 chip->position_fix = check_position_fix(chip, position_fix[dev]);
2028 check_probe_mask(chip, dev);
2029
2030 chip->single_cmd = single_cmd;
2031
2032 if (bdl_pos_adj[dev] < 0) {
2033 switch (chip->driver_type) {
2034 case AZX_DRIVER_ICH:
2035 bdl_pos_adj[dev] = 1;
2036 break;
2037 default:
2038 bdl_pos_adj[dev] = 32;
2039 break;
2040 }
2041 }
2042
2043 #if BITS_PER_LONG != 64
2044 /* Fix up base address on ULI M5461 */
2045 if (chip->driver_type == AZX_DRIVER_ULI) {
2046 u16 tmp3;
2047 pci_read_config_word(pci, 0x40, &tmp3);
2048 pci_write_config_word(pci, 0x40, tmp3 | 0x10);
2049 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0);
2050 }
2051 #endif
2052
2053 err = pci_request_regions(pci, "ICH HD audio");
2054 if (err < 0) {
2055 kfree(chip);
2056 pci_disable_device(pci);
2057 return err;
2058 }
2059
2060 chip->addr = pci_resource_start(pci, 0);
2061 chip->remap_addr = ioremap_nocache(chip->addr, pci_resource_len(pci,0));
2062 if (chip->remap_addr == NULL) {
2063 snd_printk(KERN_ERR SFX "ioremap error\n");
2064 err = -ENXIO;
2065 goto errout;
2066 }
2067
2068 if (chip->msi)
2069 if (pci_enable_msi(pci) < 0)
2070 chip->msi = 0;
2071
2072 if (azx_acquire_irq(chip, 0) < 0) {
2073 err = -EBUSY;
2074 goto errout;
2075 }
2076
2077 pci_set_master(pci);
2078 synchronize_irq(chip->irq);
2079
2080 gcap = azx_readw(chip, GCAP);
2081 snd_printdd("chipset global capabilities = 0x%x\n", gcap);
2082
2083 /* allow 64bit DMA address if supported by H/W */
2084 if ((gcap & 0x01) && !pci_set_dma_mask(pci, DMA_64BIT_MASK))
2085 pci_set_consistent_dma_mask(pci, DMA_64BIT_MASK);
2086
2087 /* read number of streams from GCAP register instead of using
2088 * hardcoded value
2089 */
2090 chip->capture_streams = (gcap >> 8) & 0x0f;
2091 chip->playback_streams = (gcap >> 12) & 0x0f;
2092 if (!chip->playback_streams && !chip->capture_streams) {
2093 /* gcap didn't give any info, switching to old method */
2094
2095 switch (chip->driver_type) {
2096 case AZX_DRIVER_ULI:
2097 chip->playback_streams = ULI_NUM_PLAYBACK;
2098 chip->capture_streams = ULI_NUM_CAPTURE;
2099 break;
2100 case AZX_DRIVER_ATIHDMI:
2101 chip->playback_streams = ATIHDMI_NUM_PLAYBACK;
2102 chip->capture_streams = ATIHDMI_NUM_CAPTURE;
2103 break;
2104 default:
2105 chip->playback_streams = ICH6_NUM_PLAYBACK;
2106 chip->capture_streams = ICH6_NUM_CAPTURE;
2107 break;
2108 }
2109 }
2110 chip->capture_index_offset = 0;
2111 chip->playback_index_offset = chip->capture_streams;
2112 chip->num_streams = chip->playback_streams + chip->capture_streams;
2113 chip->azx_dev = kcalloc(chip->num_streams, sizeof(*chip->azx_dev),
2114 GFP_KERNEL);
2115 if (!chip->azx_dev) {
2116 snd_printk(KERN_ERR "cannot malloc azx_dev\n");
2117 goto errout;
2118 }
2119
2120 for (i = 0; i < chip->num_streams; i++) {
2121 /* allocate memory for the BDL for each stream */
2122 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
2123 snd_dma_pci_data(chip->pci),
2124 BDL_SIZE, &chip->azx_dev[i].bdl);
2125 if (err < 0) {
2126 snd_printk(KERN_ERR SFX "cannot allocate BDL\n");
2127 goto errout;
2128 }
2129 }
2130 /* allocate memory for the position buffer */
2131 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
2132 snd_dma_pci_data(chip->pci),
2133 chip->num_streams * 8, &chip->posbuf);
2134 if (err < 0) {
2135 snd_printk(KERN_ERR SFX "cannot allocate posbuf\n");
2136 goto errout;
2137 }
2138 /* allocate CORB/RIRB */
2139 if (!chip->single_cmd) {
2140 err = azx_alloc_cmd_io(chip);
2141 if (err < 0)
2142 goto errout;
2143 }
2144
2145 /* initialize streams */
2146 azx_init_stream(chip);
2147
2148 /* initialize chip */
2149 azx_init_pci(chip);
2150 azx_init_chip(chip);
2151
2152 /* codec detection */
2153 if (!chip->codec_mask) {
2154 snd_printk(KERN_ERR SFX "no codecs found!\n");
2155 err = -ENODEV;
2156 goto errout;
2157 }
2158
2159 err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
2160 if (err <0) {
2161 snd_printk(KERN_ERR SFX "Error creating device [card]!\n");
2162 goto errout;
2163 }
2164
2165 strcpy(card->driver, "HDA-Intel");
2166 strcpy(card->shortname, driver_short_names[chip->driver_type]);
2167 sprintf(card->longname, "%s at 0x%lx irq %i",
2168 card->shortname, chip->addr, chip->irq);
2169
2170 *rchip = chip;
2171 return 0;
2172
2173 errout:
2174 azx_free(chip);
2175 return err;
2176 }
2177
2178 static void power_down_all_codecs(struct azx *chip)
2179 {
2180 #ifdef CONFIG_SND_HDA_POWER_SAVE
2181 /* The codecs were powered up in snd_hda_codec_new().
2182 * Now all initialization done, so turn them down if possible
2183 */
2184 struct hda_codec *codec;
2185 list_for_each_entry(codec, &chip->bus->codec_list, list) {
2186 snd_hda_power_down(codec);
2187 }
2188 #endif
2189 }
2190
2191 static int __devinit azx_probe(struct pci_dev *pci,
2192 const struct pci_device_id *pci_id)
2193 {
2194 static int dev;
2195 struct snd_card *card;
2196 struct azx *chip;
2197 int err;
2198
2199 if (dev >= SNDRV_CARDS)
2200 return -ENODEV;
2201 if (!enable[dev]) {
2202 dev++;
2203 return -ENOENT;
2204 }
2205
2206 card = snd_card_new(index[dev], id[dev], THIS_MODULE, 0);
2207 if (!card) {
2208 snd_printk(KERN_ERR SFX "Error creating card!\n");
2209 return -ENOMEM;
2210 }
2211
2212 err = azx_create(card, pci, dev, pci_id->driver_data, &chip);
2213 if (err < 0) {
2214 snd_card_free(card);
2215 return err;
2216 }
2217 card->private_data = chip;
2218
2219 /* create codec instances */
2220 err = azx_codec_create(chip, model[dev], probe_mask[dev]);
2221 if (err < 0) {
2222 snd_card_free(card);
2223 return err;
2224 }
2225
2226 /* create PCM streams */
2227 err = azx_pcm_create(chip);
2228 if (err < 0) {
2229 snd_card_free(card);
2230 return err;
2231 }
2232
2233 /* create mixer controls */
2234 err = azx_mixer_create(chip);
2235 if (err < 0) {
2236 snd_card_free(card);
2237 return err;
2238 }
2239
2240 snd_card_set_dev(card, &pci->dev);
2241
2242 err = snd_card_register(card);
2243 if (err < 0) {
2244 snd_card_free(card);
2245 return err;
2246 }
2247
2248 pci_set_drvdata(pci, card);
2249 chip->running = 1;
2250 power_down_all_codecs(chip);
2251
2252 dev++;
2253 return err;
2254 }
2255
2256 static void __devexit azx_remove(struct pci_dev *pci)
2257 {
2258 snd_card_free(pci_get_drvdata(pci));
2259 pci_set_drvdata(pci, NULL);
2260 }
2261
2262 /* PCI IDs */
2263 static struct pci_device_id azx_ids[] = {
2264 /* ICH 6..10 */
2265 { PCI_DEVICE(0x8086, 0x2668), .driver_data = AZX_DRIVER_ICH },
2266 { PCI_DEVICE(0x8086, 0x27d8), .driver_data = AZX_DRIVER_ICH },
2267 { PCI_DEVICE(0x8086, 0x269a), .driver_data = AZX_DRIVER_ICH },
2268 { PCI_DEVICE(0x8086, 0x284b), .driver_data = AZX_DRIVER_ICH },
2269 { PCI_DEVICE(0x8086, 0x2911), .driver_data = AZX_DRIVER_ICH },
2270 { PCI_DEVICE(0x8086, 0x293e), .driver_data = AZX_DRIVER_ICH },
2271 { PCI_DEVICE(0x8086, 0x293f), .driver_data = AZX_DRIVER_ICH },
2272 { PCI_DEVICE(0x8086, 0x3a3e), .driver_data = AZX_DRIVER_ICH },
2273 { PCI_DEVICE(0x8086, 0x3a6e), .driver_data = AZX_DRIVER_ICH },
2274 /* PCH */
2275 { PCI_DEVICE(0x8086, 0x3b56), .driver_data = AZX_DRIVER_ICH },
2276 /* SCH */
2277 { PCI_DEVICE(0x8086, 0x811b), .driver_data = AZX_DRIVER_SCH },
2278 /* ATI SB 450/600 */
2279 { PCI_DEVICE(0x1002, 0x437b), .driver_data = AZX_DRIVER_ATI },
2280 { PCI_DEVICE(0x1002, 0x4383), .driver_data = AZX_DRIVER_ATI },
2281 /* ATI HDMI */
2282 { PCI_DEVICE(0x1002, 0x793b), .driver_data = AZX_DRIVER_ATIHDMI },
2283 { PCI_DEVICE(0x1002, 0x7919), .driver_data = AZX_DRIVER_ATIHDMI },
2284 { PCI_DEVICE(0x1002, 0x960f), .driver_data = AZX_DRIVER_ATIHDMI },
2285 { PCI_DEVICE(0x1002, 0x970f), .driver_data = AZX_DRIVER_ATIHDMI },
2286 { PCI_DEVICE(0x1002, 0xaa00), .driver_data = AZX_DRIVER_ATIHDMI },
2287 { PCI_DEVICE(0x1002, 0xaa08), .driver_data = AZX_DRIVER_ATIHDMI },
2288 { PCI_DEVICE(0x1002, 0xaa10), .driver_data = AZX_DRIVER_ATIHDMI },
2289 { PCI_DEVICE(0x1002, 0xaa18), .driver_data = AZX_DRIVER_ATIHDMI },
2290 { PCI_DEVICE(0x1002, 0xaa20), .driver_data = AZX_DRIVER_ATIHDMI },
2291 { PCI_DEVICE(0x1002, 0xaa28), .driver_data = AZX_DRIVER_ATIHDMI },
2292 { PCI_DEVICE(0x1002, 0xaa30), .driver_data = AZX_DRIVER_ATIHDMI },
2293 { PCI_DEVICE(0x1002, 0xaa38), .driver_data = AZX_DRIVER_ATIHDMI },
2294 { PCI_DEVICE(0x1002, 0xaa40), .driver_data = AZX_DRIVER_ATIHDMI },
2295 { PCI_DEVICE(0x1002, 0xaa48), .driver_data = AZX_DRIVER_ATIHDMI },
2296 /* VIA VT8251/VT8237A */
2297 { PCI_DEVICE(0x1106, 0x3288), .driver_data = AZX_DRIVER_VIA },
2298 /* SIS966 */
2299 { PCI_DEVICE(0x1039, 0x7502), .driver_data = AZX_DRIVER_SIS },
2300 /* ULI M5461 */
2301 { PCI_DEVICE(0x10b9, 0x5461), .driver_data = AZX_DRIVER_ULI },
2302 /* NVIDIA MCP */
2303 { PCI_DEVICE(0x10de, 0x026c), .driver_data = AZX_DRIVER_NVIDIA },
2304 { PCI_DEVICE(0x10de, 0x0371), .driver_data = AZX_DRIVER_NVIDIA },
2305 { PCI_DEVICE(0x10de, 0x03e4), .driver_data = AZX_DRIVER_NVIDIA },
2306 { PCI_DEVICE(0x10de, 0x03f0), .driver_data = AZX_DRIVER_NVIDIA },
2307 { PCI_DEVICE(0x10de, 0x044a), .driver_data = AZX_DRIVER_NVIDIA },
2308 { PCI_DEVICE(0x10de, 0x044b), .driver_data = AZX_DRIVER_NVIDIA },
2309 { PCI_DEVICE(0x10de, 0x055c), .driver_data = AZX_DRIVER_NVIDIA },
2310 { PCI_DEVICE(0x10de, 0x055d), .driver_data = AZX_DRIVER_NVIDIA },
2311 { PCI_DEVICE(0x10de, 0x0774), .driver_data = AZX_DRIVER_NVIDIA },
2312 { PCI_DEVICE(0x10de, 0x0775), .driver_data = AZX_DRIVER_NVIDIA },
2313 { PCI_DEVICE(0x10de, 0x0776), .driver_data = AZX_DRIVER_NVIDIA },
2314 { PCI_DEVICE(0x10de, 0x0777), .driver_data = AZX_DRIVER_NVIDIA },
2315 { PCI_DEVICE(0x10de, 0x07fc), .driver_data = AZX_DRIVER_NVIDIA },
2316 { PCI_DEVICE(0x10de, 0x07fd), .driver_data = AZX_DRIVER_NVIDIA },
2317 { PCI_DEVICE(0x10de, 0x0ac0), .driver_data = AZX_DRIVER_NVIDIA },
2318 { PCI_DEVICE(0x10de, 0x0ac1), .driver_data = AZX_DRIVER_NVIDIA },
2319 { PCI_DEVICE(0x10de, 0x0ac2), .driver_data = AZX_DRIVER_NVIDIA },
2320 { PCI_DEVICE(0x10de, 0x0ac3), .driver_data = AZX_DRIVER_NVIDIA },
2321 { PCI_DEVICE(0x10de, 0x0bd4), .driver_data = AZX_DRIVER_NVIDIA },
2322 { PCI_DEVICE(0x10de, 0x0bd5), .driver_data = AZX_DRIVER_NVIDIA },
2323 { PCI_DEVICE(0x10de, 0x0bd6), .driver_data = AZX_DRIVER_NVIDIA },
2324 { PCI_DEVICE(0x10de, 0x0bd7), .driver_data = AZX_DRIVER_NVIDIA },
2325 /* Teradici */
2326 { PCI_DEVICE(0x6549, 0x1200), .driver_data = AZX_DRIVER_TERA },
2327 { 0, }
2328 };
2329 MODULE_DEVICE_TABLE(pci, azx_ids);
2330
2331 /* pci_driver definition */
2332 static struct pci_driver driver = {
2333 .name = "HDA Intel",
2334 .id_table = azx_ids,
2335 .probe = azx_probe,
2336 .remove = __devexit_p(azx_remove),
2337 #ifdef CONFIG_PM
2338 .suspend = azx_suspend,
2339 .resume = azx_resume,
2340 #endif
2341 };
2342
2343 static int __init alsa_card_azx_init(void)
2344 {
2345 return pci_register_driver(&driver);
2346 }
2347
2348 static void __exit alsa_card_azx_exit(void)
2349 {
2350 pci_unregister_driver(&driver);
2351 }
2352
2353 module_init(alsa_card_azx_init)
2354 module_exit(alsa_card_azx_exit)
2355
This page was automatically generated by the
LXR engine.
Visit the LXR main site for more
information.