1 /*
2 =========================================================================
3 r8169.c: A RealTek RTL-8169 Gigabit Ethernet driver for Linux kernel 2.4.x.
4 --------------------------------------------------------------------
5
6 History:
7 Feb 4 2002 - created initially by ShuChen <shuchen@realtek.com.tw>.
8 May 20 2002 - Add link status force-mode and TBI mode support.
9 2004 - Massive updates. See kernel SCM system for details.
10 =========================================================================
11 1. [DEPRECATED: use ethtool instead] The media can be forced in 5 modes.
12 Command: 'insmod r8169 media = SET_MEDIA'
13 Ex: 'insmod r8169 media = 0x04' will force PHY to operate in 100Mpbs Half-duplex.
14
15 SET_MEDIA can be:
16 _10_Half = 0x01
17 _10_Full = 0x02
18 _100_Half = 0x04
19 _100_Full = 0x08
20 _1000_Full = 0x10
21
22 2. Support TBI mode.
23 =========================================================================
24 VERSION 1.1 <2002/10/4>
25
26 The bit4:0 of MII register 4 is called "selector field", and have to be
27 00001b to indicate support of IEEE std 802.3 during NWay process of
28 exchanging Link Code Word (FLP).
29
30 VERSION 1.2 <2002/11/30>
31
32 - Large style cleanup
33 - Use ether_crc in stock kernel (linux/crc32.h)
34 - Copy mc_filter setup code from 8139cp
35 (includes an optimization, and avoids set_bit use)
36
37 VERSION 1.6LK <2004/04/14>
38
39 - Merge of Realtek's version 1.6
40 - Conversion to DMA API
41 - Suspend/resume
42 - Endianness
43 - Misc Rx/Tx bugs
44
45 VERSION 2.2LK <2005/01/25>
46
47 - RX csum, TX csum/SG, TSO
48 - VLAN
49 - baby (< 7200) Jumbo frames support
50 - Merge of Realtek's version 2.2 (new phy)
51 */
52
53 #include <linux/module.h>
54 #include <linux/moduleparam.h>
55 #include <linux/pci.h>
56 #include <linux/netdevice.h>
57 #include <linux/etherdevice.h>
58 #include <linux/delay.h>
59 #include <linux/ethtool.h>
60 #include <linux/mii.h>
61 #include <linux/if_vlan.h>
62 #include <linux/crc32.h>
63 #include <linux/in.h>
64 #include <linux/ip.h>
65 #include <linux/tcp.h>
66 #include <linux/init.h>
67 #include <linux/dma-mapping.h>
68
69 #include <asm/io.h>
70 #include <asm/irq.h>
71
72 #ifdef CONFIG_R8169_NAPI
73 #define NAPI_SUFFIX "-NAPI"
74 #else
75 #define NAPI_SUFFIX ""
76 #endif
77
78 #define RTL8169_VERSION "2.2LK" NAPI_SUFFIX
79 #define MODULENAME "r8169"
80 #define PFX MODULENAME ": "
81
82 #ifdef RTL8169_DEBUG
83 #define assert(expr) \
84 if(!(expr)) { \
85 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
86 #expr,__FILE__,__FUNCTION__,__LINE__); \
87 }
88 #define dprintk(fmt, args...) do { printk(PFX fmt, ## args); } while (0)
89 #else
90 #define assert(expr) do {} while (0)
91 #define dprintk(fmt, args...) do {} while (0)
92 #endif /* RTL8169_DEBUG */
93
94 #define R8169_MSG_DEFAULT \
95 (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
96
97 #define TX_BUFFS_AVAIL(tp) \
98 (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx - 1)
99
100 #ifdef CONFIG_R8169_NAPI
101 #define rtl8169_rx_skb netif_receive_skb
102 #define rtl8169_rx_hwaccel_skb vlan_hwaccel_receive_skb
103 #define rtl8169_rx_quota(count, quota) min(count, quota)
104 #else
105 #define rtl8169_rx_skb netif_rx
106 #define rtl8169_rx_hwaccel_skb vlan_hwaccel_rx
107 #define rtl8169_rx_quota(count, quota) count
108 #endif
109
110 /* media options */
111 #define MAX_UNITS 8
112 static int media[MAX_UNITS] = { -1, -1, -1, -1, -1, -1, -1, -1 };
113 static int num_media = 0;
114
115 /* Maximum events (Rx packets, etc.) to handle at each interrupt. */
116 static const int max_interrupt_work = 20;
117
118 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
119 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
120 static const int multicast_filter_limit = 32;
121
122 /* MAC address length */
123 #define MAC_ADDR_LEN 6
124
125 #define RX_FIFO_THRESH 7 /* 7 means NO threshold, Rx buffer level before first PCI xfer. */
126 #define RX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
127 #define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
128 #define EarlyTxThld 0x3F /* 0x3F means NO early transmit */
129 #define RxPacketMaxSize 0x3FE8 /* 16K - 1 - ETH_HLEN - VLAN - CRC... */
130 #define SafeMtu 0x1c20 /* ... actually life sucks beyond ~7k */
131 #define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
132
133 #define R8169_REGS_SIZE 256
134 #define R8169_NAPI_WEIGHT 64
135 #define NUM_TX_DESC 64 /* Number of Tx descriptor registers */
136 #define NUM_RX_DESC 256 /* Number of Rx descriptor registers */
137 #define RX_BUF_SIZE 1536 /* Rx Buffer size */
138 #define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc))
139 #define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc))
140
141 #define RTL8169_TX_TIMEOUT (6*HZ)
142 #define RTL8169_PHY_TIMEOUT (10*HZ)
143
144 /* write/read MMIO register */
145 #define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg))
146 #define RTL_W16(reg, val16) writew ((val16), ioaddr + (reg))
147 #define RTL_W32(reg, val32) writel ((val32), ioaddr + (reg))
148 #define RTL_R8(reg) readb (ioaddr + (reg))
149 #define RTL_R16(reg) readw (ioaddr + (reg))
150 #define RTL_R32(reg) ((unsigned long) readl (ioaddr + (reg)))
151
152 enum mac_version {
153 RTL_GIGA_MAC_VER_01 = 0x00,
154 RTL_GIGA_MAC_VER_02 = 0x01,
155 RTL_GIGA_MAC_VER_03 = 0x02,
156 RTL_GIGA_MAC_VER_04 = 0x03,
157 RTL_GIGA_MAC_VER_05 = 0x04,
158 RTL_GIGA_MAC_VER_06 = 0x06,
159 RTL_GIGA_MAC_VER_11 = 0x0b,
160 RTL_GIGA_MAC_VER_12 = 0x0c,
161 RTL_GIGA_MAC_VER_13 = 0x0d,
162 RTL_GIGA_MAC_VER_14 = 0x0e,
163 RTL_GIGA_MAC_VER_15 = 0x0f,
164 RTL_GIGA_MAC_VER_16 = 0x11,
165 RTL_GIGA_MAC_VER_17 = 0x10,
166 RTL_GIGA_MAC_VER_18 = 0x12,
167 RTL_GIGA_MAC_VER_19 = 0x13,
168 RTL_GIGA_MAC_VER_20 = 0x14
169 };
170
171 enum phy_version {
172 RTL_GIGA_PHY_VER_C = 0x03, /* PHY Reg 0x03 bit0-3 == 0x0000 */
173 RTL_GIGA_PHY_VER_D = 0x04, /* PHY Reg 0x03 bit0-3 == 0x0000 */
174 RTL_GIGA_PHY_VER_E = 0x05, /* PHY Reg 0x03 bit0-3 == 0x0000 */
175 RTL_GIGA_PHY_VER_F = 0x06, /* PHY Reg 0x03 bit0-3 == 0x0001 */
176 RTL_GIGA_PHY_VER_G = 0x07, /* PHY Reg 0x03 bit0-3 == 0x0002 */
177 RTL_GIGA_PHY_VER_H = 0x08, /* PHY Reg 0x03 bit0-3 == 0x0003 */
178 };
179
180
181 #define _R(NAME,MAC,MASK) \
182 { .name = NAME, .mac_version = MAC, .RxConfigMask = MASK }
183
184 static const struct {
185 const char *name;
186 u8 mac_version;
187 u32 RxConfigMask; /* Clears the bits supported by this chip */
188 } rtl_chip_info[] = {
189 _R("RTL8169", RTL_GIGA_MAC_VER_01, 0xff7e1880),
190 _R("RTL8169s/8110s", RTL_GIGA_MAC_VER_02, 0xff7e1880),
191 _R("RTL8169s/8110s", RTL_GIGA_MAC_VER_03, 0xff7e1880),
192 _R("RTL8169sb/8110sb", RTL_GIGA_MAC_VER_04, 0xff7e1880),
193 _R("RTL8169sc/8110sc", RTL_GIGA_MAC_VER_05, 0xff7e1880),
194 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_11, 0xff7e1880), // PCI-E
195 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_12, 0xff7e1880), // PCI-E
196 _R("RTL8101e", RTL_GIGA_MAC_VER_13, 0xff7e1880), // PCI-E 8139
197 _R("RTL8100e", RTL_GIGA_MAC_VER_14, 0xff7e1880), // PCI-E 8139
198 _R("RTL8100e", RTL_GIGA_MAC_VER_15, 0xff7e1880), // PCI-E 8139
199 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_17, 0xff7e1880), // PCI-E
200 _R("RTL8101e", RTL_GIGA_MAC_VER_16, 0xff7e1880), // PCI-E
201 _R("RTL8168cp/8111cp", RTL_GIGA_MAC_VER_18, 0xff7e1880), // PCI-E
202 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_19, 0xff7e1880), // PCI-E
203 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_20, 0xff7e1880) // PCI-E
204 };
205 #undef _R
206
207 enum cfg_version {
208 RTL_CFG_0 = 0x00,
209 RTL_CFG_1,
210 RTL_CFG_2
211 };
212
213 static const struct {
214 unsigned int region;
215 unsigned int align;
216 } rtl_cfg_info[] = {
217 [RTL_CFG_0] = { 1, NET_IP_ALIGN },
218 [RTL_CFG_1] = { 2, NET_IP_ALIGN },
219 [RTL_CFG_2] = { 2, 8 }
220 };
221
222 static struct pci_device_id rtl8169_pci_tbl[] = {
223 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8129), 0, 0, RTL_CFG_0 },
224 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8136), 0, 0, RTL_CFG_2 },
225 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8167), 0, 0, RTL_CFG_0 },
226 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8168), 0, 0, RTL_CFG_2 },
227 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8169), 0, 0, RTL_CFG_0 },
228 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4300), 0, 0, RTL_CFG_0 },
229 { PCI_DEVICE(0x1259, 0xc107), 0, 0, RTL_CFG_0 },
230 { PCI_DEVICE(0x16ec, 0x0116), 0, 0, RTL_CFG_0 },
231 { PCI_VENDOR_ID_LINKSYS, 0x1032,
232 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
233 {0,},
234 };
235
236 MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
237
238 static int rx_copybreak = 200;
239 static int use_dac;
240 static struct {
241 u32 msg_enable;
242 } debug = { -1 };
243
244 enum RTL8169_registers {
245 MAC0 = 0, /* Ethernet hardware address. */
246 MAR0 = 8, /* Multicast filter. */
247 CounterAddrLow = 0x10,
248 CounterAddrHigh = 0x14,
249 TxDescStartAddrLow = 0x20,
250 TxDescStartAddrHigh = 0x24,
251 TxHDescStartAddrLow = 0x28,
252 TxHDescStartAddrHigh = 0x2c,
253 FLASH = 0x30,
254 ERSR = 0x36,
255 ChipCmd = 0x37,
256 TxPoll = 0x38,
257 IntrMask = 0x3C,
258 IntrStatus = 0x3E,
259 TxConfig = 0x40,
260 RxConfig = 0x44,
261 RxMissed = 0x4C,
262 Cfg9346 = 0x50,
263 Config0 = 0x51,
264 Config1 = 0x52,
265 Config2 = 0x53,
266 Config3 = 0x54,
267 Config4 = 0x55,
268 Config5 = 0x56,
269 MultiIntr = 0x5C,
270 PHYAR = 0x60,
271 TBICSR = 0x64,
272 TBI_ANAR = 0x68,
273 TBI_LPAR = 0x6A,
274 PHYstatus = 0x6C,
275 RxMaxSize = 0xDA,
276 CPlusCmd = 0xE0,
277 IntrMitigate = 0xE2,
278 RxDescAddrLow = 0xE4,
279 RxDescAddrHigh = 0xE8,
280 EarlyTxThres = 0xEC,
281 FuncEvent = 0xF0,
282 FuncEventMask = 0xF4,
283 FuncPresetState = 0xF8,
284 FuncForceEvent = 0xFC,
285 };
286
287 enum RTL8169_register_content {
288 /* InterruptStatusBits */
289 SYSErr = 0x8000,
290 PCSTimeout = 0x4000,
291 SWInt = 0x0100,
292 TxDescUnavail = 0x80,
293 RxFIFOOver = 0x40,
294 LinkChg = 0x20,
295 RxOverflow = 0x10,
296 TxErr = 0x08,
297 TxOK = 0x04,
298 RxErr = 0x02,
299 RxOK = 0x01,
300
301 /* RxStatusDesc */
302 RxFOVF = (1 << 23),
303 RxRWT = (1 << 22),
304 RxRES = (1 << 21),
305 RxRUNT = (1 << 20),
306 RxCRC = (1 << 19),
307
308 /* ChipCmdBits */
309 CmdReset = 0x10,
310 CmdRxEnb = 0x08,
311 CmdTxEnb = 0x04,
312 RxBufEmpty = 0x01,
313
314 /* Cfg9346Bits */
315 Cfg9346_Lock = 0x00,
316 Cfg9346_Unlock = 0xC0,
317
318 /* rx_mode_bits */
319 AcceptErr = 0x20,
320 AcceptRunt = 0x10,
321 AcceptBroadcast = 0x08,
322 AcceptMulticast = 0x04,
323 AcceptMyPhys = 0x02,
324 AcceptAllPhys = 0x01,
325
326 /* RxConfigBits */
327 RxCfgFIFOShift = 13,
328 RxCfgDMAShift = 8,
329
330 /* TxConfigBits */
331 TxInterFrameGapShift = 24,
332 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
333
334 /* Config1 register p.24 */
335 PMEnable = (1 << 0), /* Power Management Enable */
336
337 /* Config3 register p.25 */
338 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */
339 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */
340
341 /* Config5 register p.27 */
342 BWF = (1 << 6), /* Accept Broadcast wakeup frame */
343 MWF = (1 << 5), /* Accept Multicast wakeup frame */
344 UWF = (1 << 4), /* Accept Unicast wakeup frame */
345 LanWake = (1 << 1), /* LanWake enable/disable */
346 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */
347
348 /* TBICSR p.28 */
349 TBIReset = 0x80000000,
350 TBILoopback = 0x40000000,
351 TBINwEnable = 0x20000000,
352 TBINwRestart = 0x10000000,
353 TBILinkOk = 0x02000000,
354 TBINwComplete = 0x01000000,
355
356 /* CPlusCmd p.31 */
357 RxVlan = (1 << 6),
358 RxChkSum = (1 << 5),
359 PCIDAC = (1 << 4),
360 PCIMulRW = (1 << 3),
361
362 /* rtl8169_PHYstatus */
363 TBI_Enable = 0x80,
364 TxFlowCtrl = 0x40,
365 RxFlowCtrl = 0x20,
366 _1000bpsF = 0x10,
367 _100bps = 0x08,
368 _10bps = 0x04,
369 LinkStatus = 0x02,
370 FullDup = 0x01,
371
372 /* _MediaType */
373 _10_Half = 0x01,
374 _10_Full = 0x02,
375 _100_Half = 0x04,
376 _100_Full = 0x08,
377 _1000_Full = 0x10,
378
379 /* _TBICSRBit */
380 TBILinkOK = 0x02000000,
381
382 /* DumpCounterCommand */
383 CounterDump = 0x8,
384 };
385
386 enum _DescStatusBit {
387 DescOwn = (1 << 31), /* Descriptor is owned by NIC */
388 RingEnd = (1 << 30), /* End of descriptor ring */
389 FirstFrag = (1 << 29), /* First segment of a packet */
390 LastFrag = (1 << 28), /* Final segment of a packet */
391
392 /* Tx private */
393 LargeSend = (1 << 27), /* TCP Large Send Offload (TSO) */
394 MSSShift = 16, /* MSS value position */
395 MSSMask = 0xfff, /* MSS value + LargeSend bit: 12 bits */
396 IPCS = (1 << 18), /* Calculate IP checksum */
397 UDPCS = (1 << 17), /* Calculate UDP/IP checksum */
398 TCPCS = (1 << 16), /* Calculate TCP/IP checksum */
399 TxVlanTag = (1 << 17), /* Add VLAN tag */
400
401 /* Rx private */
402 PID1 = (1 << 18), /* Protocol ID bit 1/2 */
403 PID0 = (1 << 17), /* Protocol ID bit 2/2 */
404
405 #define RxProtoUDP (PID1)
406 #define RxProtoTCP (PID0)
407 #define RxProtoIP (PID1 | PID0)
408 #define RxProtoMask RxProtoIP
409
410 IPFail = (1 << 16), /* IP checksum failed */
411 UDPFail = (1 << 15), /* UDP/IP checksum failed */
412 TCPFail = (1 << 14), /* TCP/IP checksum failed */
413 RxVlanTag = (1 << 16), /* VLAN tag available */
414 };
415
416 #define RsvdMask 0x3fffc000
417
418 struct TxDesc {
419 u32 opts1;
420 u32 opts2;
421 u64 addr;
422 };
423
424 struct RxDesc {
425 u32 opts1;
426 u32 opts2;
427 u64 addr;
428 };
429
430 struct ring_info {
431 struct sk_buff *skb;
432 u32 len;
433 u8 __pad[sizeof(void *) - sizeof(u32)];
434 };
435
436 struct rtl8169_private {
437 void __iomem *mmio_addr; /* memory map physical address */
438 struct pci_dev *pci_dev; /* Index of PCI device */
439 struct net_device *dev;
440 struct net_device_stats stats; /* statistics of net device */
441 spinlock_t lock; /* spin lock flag */
442 u32 msg_enable;
443 int chipset;
444 int mac_version;
445 int phy_version;
446 u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
447 u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
448 u32 dirty_rx;
449 u32 dirty_tx;
450 struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */
451 struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */
452 dma_addr_t TxPhyAddr;
453 dma_addr_t RxPhyAddr;
454 struct sk_buff *Rx_skbuff[NUM_RX_DESC]; /* Rx data buffers */
455 struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */
456 unsigned align;
457 unsigned rx_buf_sz;
458 struct timer_list timer;
459 u16 cp_cmd;
460 u16 intr_mask;
461 int phy_auto_nego_reg;
462 int phy_1000_ctrl_reg;
463 #ifdef CONFIG_R8169_VLAN
464 struct vlan_group *vlgrp;
465 #endif
466 int (*set_speed)(struct net_device *, u8 autoneg, u16 speed, u8 duplex);
467 void (*get_settings)(struct net_device *, struct ethtool_cmd *);
468 void (*phy_reset_enable)(void __iomem *);
469 unsigned int (*phy_reset_pending)(void __iomem *);
470 unsigned int (*link_ok)(void __iomem *);
471 struct work_struct task;
472 unsigned wol_enabled : 1;
473 };
474
475 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
476 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
477 module_param_array(media, int, &num_media, 0);
478 MODULE_PARM_DESC(media, "force phy operation. Deprecated by ethtool (8).");
479 module_param(rx_copybreak, int, 0);
480 MODULE_PARM_DESC(rx_copybreak, "Copy breakpoint for copy-only-tiny-frames");
481 module_param(use_dac, int, 0);
482 MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
483 module_param_named(debug, debug.msg_enable, int, 0);
484 MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
485 MODULE_LICENSE("GPL");
486 MODULE_VERSION(RTL8169_VERSION);
487
488 static int rtl8169_open(struct net_device *dev);
489 static int rtl8169_start_xmit(struct sk_buff *skb, struct net_device *dev);
490 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance,
491 struct pt_regs *regs);
492 static int rtl8169_init_ring(struct net_device *dev);
493 static void rtl8169_hw_start(struct net_device *dev);
494 static int rtl8169_close(struct net_device *dev);
495 static void rtl8169_set_rx_mode(struct net_device *dev);
496 static void rtl8169_tx_timeout(struct net_device *dev);
497 static struct net_device_stats *rtl8169_get_stats(struct net_device *dev);
498 static int rtl8169_rx_interrupt(struct net_device *, struct rtl8169_private *,
499 void __iomem *);
500 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu);
501 static void rtl8169_down(struct net_device *dev);
502
503 #ifdef CONFIG_R8169_NAPI
504 static int rtl8169_poll(struct net_device *dev, int *budget);
505 #endif
506
507 static const u16 rtl8169_intr_mask =
508 SYSErr | LinkChg | RxOverflow | RxFIFOOver | TxErr | TxOK | RxErr | RxOK;
509 static const u16 rtl8169_napi_event =
510 RxOK | RxOverflow | RxFIFOOver | TxOK | TxErr;
511 static const unsigned int rtl8169_rx_config =
512 (RX_FIFO_THRESH << RxCfgFIFOShift) | (RX_DMA_BURST << RxCfgDMAShift);
513
514 static void mdio_write(void __iomem *ioaddr, int RegAddr, int value)
515 {
516 int i;
517
518 RTL_W32(PHYAR, 0x80000000 | (RegAddr & 0xFF) << 16 | value);
519
520 for (i = 20; i > 0; i--) {
521 /* Check if the RTL8169 has completed writing to the specified MII register */
522 if (!(RTL_R32(PHYAR) & 0x80000000))
523 break;
524 udelay(25);
525 }
526 }
527
528 static int mdio_read(void __iomem *ioaddr, int RegAddr)
529 {
530 int i, value = -1;
531
532 RTL_W32(PHYAR, 0x0 | (RegAddr & 0xFF) << 16);
533
534 for (i = 20; i > 0; i--) {
535 /* Check if the RTL8169 has completed retrieving data from the specified MII register */
536 if (RTL_R32(PHYAR) & 0x80000000) {
537 value = (int) (RTL_R32(PHYAR) & 0xFFFF);
538 break;
539 }
540 udelay(25);
541 }
542 return value;
543 }
544
545 static void rtl8169_irq_mask_and_ack(void __iomem *ioaddr)
546 {
547 RTL_W16(IntrMask, 0x0000);
548
549 RTL_W16(IntrStatus, 0xffff);
550 }
551
552 static void rtl8169_asic_down(void __iomem *ioaddr)
553 {
554 RTL_W8(ChipCmd, 0x00);
555 rtl8169_irq_mask_and_ack(ioaddr);
556 RTL_R16(CPlusCmd);
557 }
558
559 static unsigned int rtl8169_tbi_reset_pending(void __iomem *ioaddr)
560 {
561 return RTL_R32(TBICSR) & TBIReset;
562 }
563
564 static unsigned int rtl8169_xmii_reset_pending(void __iomem *ioaddr)
565 {
566 return mdio_read(ioaddr, MII_BMCR) & BMCR_RESET;
567 }
568
569 static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr)
570 {
571 return RTL_R32(TBICSR) & TBILinkOk;
572 }
573
574 static unsigned int rtl8169_xmii_link_ok(void __iomem *ioaddr)
575 {
576 return RTL_R8(PHYstatus) & LinkStatus;
577 }
578
579 static void rtl8169_tbi_reset_enable(void __iomem *ioaddr)
580 {
581 RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset);
582 }
583
584 static void rtl8169_xmii_reset_enable(void __iomem *ioaddr)
585 {
586 unsigned int val;
587
588 mdio_write(ioaddr, MII_BMCR, BMCR_RESET);
589 val = mdio_read(ioaddr, MII_BMCR);
590 }
591
592 static void rtl8169_check_link_status(struct net_device *dev,
593 struct rtl8169_private *tp, void __iomem *ioaddr)
594 {
595 unsigned long flags;
596
597 spin_lock_irqsave(&tp->lock, flags);
598 if (tp->link_ok(ioaddr)) {
599 netif_carrier_on(dev);
600 if (netif_msg_ifup(tp))
601 printk(KERN_INFO PFX "%s: link up\n", dev->name);
602 } else {
603 if (netif_msg_ifdown(tp))
604 printk(KERN_INFO PFX "%s: link down\n", dev->name);
605 netif_carrier_off(dev);
606 }
607 spin_unlock_irqrestore(&tp->lock, flags);
608 }
609
610 static void rtl8169_link_option(int idx, u8 *autoneg, u16 *speed, u8 *duplex)
611 {
612 struct {
613 u16 speed;
614 u8 duplex;
615 u8 autoneg;
616 u8 media;
617 } link_settings[] = {
618 { SPEED_10, DUPLEX_HALF, AUTONEG_DISABLE, _10_Half },
619 { SPEED_10, DUPLEX_FULL, AUTONEG_DISABLE, _10_Full },
620 { SPEED_100, DUPLEX_HALF, AUTONEG_DISABLE, _100_Half },
621 { SPEED_100, DUPLEX_FULL, AUTONEG_DISABLE, _100_Full },
622 { SPEED_1000, DUPLEX_FULL, AUTONEG_DISABLE, _1000_Full },
623 /* Make TBI happy */
624 { SPEED_1000, DUPLEX_FULL, AUTONEG_ENABLE, 0xff }
625 }, *p;
626 unsigned char option;
627
628 option = ((idx < MAX_UNITS) && (idx >= 0)) ? media[idx] : 0xff;
629
630 if ((option != 0xff) && !idx && netif_msg_drv(&debug))
631 printk(KERN_WARNING PFX "media option is deprecated.\n");
632
633 for (p = link_settings; p->media != 0xff; p++) {
634 if (p->media == option)
635 break;
636 }
637 *autoneg = p->autoneg;
638 *speed = p->speed;
639 *duplex = p->duplex;
640 }
641
642 static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
643 {
644 struct rtl8169_private *tp = netdev_priv(dev);
645 void __iomem *ioaddr = tp->mmio_addr;
646 u8 options;
647
648 wol->wolopts = 0;
649
650 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
651 wol->supported = WAKE_ANY;
652
653 spin_lock_irq(&tp->lock);
654
655 options = RTL_R8(Config1);
656 if (!(options & PMEnable))
657 goto out_unlock;
658
659 options = RTL_R8(Config3);
660 if (options & LinkUp)
661 wol->wolopts |= WAKE_PHY;
662 if (options & MagicPacket)
663 wol->wolopts |= WAKE_MAGIC;
664
665 options = RTL_R8(Config5);
666 if (options & UWF)
667 wol->wolopts |= WAKE_UCAST;
668 if (options & BWF)
669 wol->wolopts |= WAKE_BCAST;
670 if (options & MWF)
671 wol->wolopts |= WAKE_MCAST;
672
673 out_unlock:
674 spin_unlock_irq(&tp->lock);
675 }
676
677 static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
678 {
679 struct rtl8169_private *tp = netdev_priv(dev);
680 void __iomem *ioaddr = tp->mmio_addr;
681 int i;
682 static struct {
683 u32 opt;
684 u16 reg;
685 u8 mask;
686 } cfg[] = {
687 { WAKE_ANY, Config1, PMEnable },
688 { WAKE_PHY, Config3, LinkUp },
689 { WAKE_MAGIC, Config3, MagicPacket },
690 { WAKE_UCAST, Config5, UWF },
691 { WAKE_BCAST, Config5, BWF },
692 { WAKE_MCAST, Config5, MWF },
693 { WAKE_ANY, Config5, LanWake }
694 };
695
696 spin_lock_irq(&tp->lock);
697
698 RTL_W8(Cfg9346, Cfg9346_Unlock);
699
700 for (i = 0; i < ARRAY_SIZE(cfg); i++) {
701 u8 options = RTL_R8(cfg[i].reg) & ~cfg[i].mask;
702 if (wol->wolopts & cfg[i].opt)
703 options |= cfg[i].mask;
704 RTL_W8(cfg[i].reg, options);
705 }
706
707 RTL_W8(Cfg9346, Cfg9346_Lock);
708
709 tp->wol_enabled = (wol->wolopts) ? 1 : 0;
710
711 spin_unlock_irq(&tp->lock);
712
713 return 0;
714 }
715
716 static void rtl8169_get_drvinfo(struct net_device *dev,
717 struct ethtool_drvinfo *info)
718 {
719 struct rtl8169_private *tp = netdev_priv(dev);
720
721 strcpy(info->driver, MODULENAME);
722 strcpy(info->version, RTL8169_VERSION);
723 strcpy(info->bus_info, pci_name(tp->pci_dev));
724 }
725
726 static int rtl8169_get_regs_len(struct net_device *dev)
727 {
728 return R8169_REGS_SIZE;
729 }
730
731 static int rtl8169_set_speed_tbi(struct net_device *dev,
732 u8 autoneg, u16 speed, u8 duplex)
733 {
734 struct rtl8169_private *tp = netdev_priv(dev);
735 void __iomem *ioaddr = tp->mmio_addr;
736 int ret = 0;
737 u32 reg;
738
739 reg = RTL_R32(TBICSR);
740 if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) &&
741 (duplex == DUPLEX_FULL)) {
742 RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart));
743 } else if (autoneg == AUTONEG_ENABLE)
744 RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart);
745 else {
746 if (netif_msg_link(tp)) {
747 printk(KERN_WARNING "%s: "
748 "incorrect speed setting refused in TBI mode\n",
749 dev->name);
750 }
751 ret = -EOPNOTSUPP;
752 }
753
754 return ret;
755 }
756
757 static int rtl8169_set_speed_xmii(struct net_device *dev,
758 u8 autoneg, u16 speed, u8 duplex)
759 {
760 struct rtl8169_private *tp = netdev_priv(dev);
761 void __iomem *ioaddr = tp->mmio_addr;
762 int auto_nego, giga_ctrl;
763
764 auto_nego = mdio_read(ioaddr, MII_ADVERTISE);
765 auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
766 ADVERTISE_100HALF | ADVERTISE_100FULL);
767 giga_ctrl = mdio_read(ioaddr, MII_CTRL1000);
768 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
769
770 if (autoneg == AUTONEG_ENABLE) {
771 auto_nego |= (ADVERTISE_10HALF | ADVERTISE_10FULL |
772 ADVERTISE_100HALF | ADVERTISE_100FULL);
773 giga_ctrl |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
774 } else {
775 if (speed == SPEED_10)
776 auto_nego |= ADVERTISE_10HALF | ADVERTISE_10FULL;
777 else if (speed == SPEED_100)
778 auto_nego |= ADVERTISE_100HALF | ADVERTISE_100FULL;
779 else if (speed == SPEED_1000)
780 giga_ctrl |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
781
782 if (duplex == DUPLEX_HALF)
783 auto_nego &= ~(ADVERTISE_10FULL | ADVERTISE_100FULL);
784
785 if (duplex == DUPLEX_FULL)
786 auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_100HALF);
787
788 /* This tweak comes straight from Realtek's driver. */
789 if ((speed == SPEED_100) && (duplex == DUPLEX_HALF) &&
790 ((tp->mac_version == RTL_GIGA_MAC_VER_13) ||
791 (tp->mac_version == RTL_GIGA_MAC_VER_16))) {
792 auto_nego = ADVERTISE_100HALF | ADVERTISE_CSMA;
793 }
794 }
795
796 /* The 8100e/8101e do Fast Ethernet only. */
797 if ((tp->mac_version == RTL_GIGA_MAC_VER_13) ||
798 (tp->mac_version == RTL_GIGA_MAC_VER_14) ||
799 (tp->mac_version == RTL_GIGA_MAC_VER_15) ||
800 (tp->mac_version == RTL_GIGA_MAC_VER_16)) {
801 if ((giga_ctrl & (ADVERTISE_1000FULL | ADVERTISE_1000HALF)) &&
802 netif_msg_link(tp)) {
803 printk(KERN_INFO "%s: PHY does not support 1000Mbps.\n",
804 dev->name);
805 }
806 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
807 }
808
809 auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
810
811 if ((tp->mac_version == RTL_GIGA_MAC_VER_12) ||
812 (tp->mac_version == RTL_GIGA_MAC_VER_17)) {
813 /* Vendor specific (0x1f) and reserved (0x0e) MII registers. */
814 mdio_write(ioaddr, 0x1f, 0x0000);
815 mdio_write(ioaddr, 0x0e, 0x0000);
816 }
817
818 tp->phy_auto_nego_reg = auto_nego;
819 tp->phy_1000_ctrl_reg = giga_ctrl;
820
821 mdio_write(ioaddr, MII_ADVERTISE, auto_nego);
822 mdio_write(ioaddr, MII_CTRL1000, giga_ctrl);
823 mdio_write(ioaddr, MII_BMCR, BMCR_ANENABLE | BMCR_ANRESTART);
824 return 0;
825 }
826
827 static int rtl8169_set_speed(struct net_device *dev,
828 u8 autoneg, u16 speed, u8 duplex)
829 {
830 struct rtl8169_private *tp = netdev_priv(dev);
831 int ret;
832
833 ret = tp->set_speed(dev, autoneg, speed, duplex);
834
835 if (netif_running(dev) && (tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL))
836 mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT);
837
838 return ret;
839 }
840
841 static int rtl8169_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
842 {
843 struct rtl8169_private *tp = netdev_priv(dev);
844 unsigned long flags;
845 int ret;
846
847 spin_lock_irqsave(&tp->lock, flags);
848 ret = rtl8169_set_speed(dev, cmd->autoneg, cmd->speed, cmd->duplex);
849 spin_unlock_irqrestore(&tp->lock, flags);
850
851 return ret;
852 }
853
854 static u32 rtl8169_get_rx_csum(struct net_device *dev)
855 {
856 struct rtl8169_private *tp = netdev_priv(dev);
857
858 return tp->cp_cmd & RxChkSum;
859 }
860
861 static int rtl8169_set_rx_csum(struct net_device *dev, u32 data)
862 {
863 struct rtl8169_private *tp = netdev_priv(dev);
864 void __iomem *ioaddr = tp->mmio_addr;
865 unsigned long flags;
866
867 spin_lock_irqsave(&tp->lock, flags);
868
869 if (data)
870 tp->cp_cmd |= RxChkSum;
871 else
872 tp->cp_cmd &= ~RxChkSum;
873
874 RTL_W16(CPlusCmd, tp->cp_cmd);
875 RTL_R16(CPlusCmd);
876
877 spin_unlock_irqrestore(&tp->lock, flags);
878
879 return 0;
880 }
881
882 #ifdef CONFIG_R8169_VLAN
883
884 static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
885 struct sk_buff *skb)
886 {
887 return (tp->vlgrp && vlan_tx_tag_present(skb)) ?
888 TxVlanTag | swab16(vlan_tx_tag_get(skb)) : 0x00;
889 }
890
891 static void rtl8169_vlan_rx_register(struct net_device *dev,
892 struct vlan_group *grp)
893 {
894 struct rtl8169_private *tp = netdev_priv(dev);
895 void __iomem *ioaddr = tp->mmio_addr;
896 unsigned long flags;
897
898 spin_lock_irqsave(&tp->lock, flags);
899 tp->vlgrp = grp;
900 if (tp->vlgrp)
901 tp->cp_cmd |= RxVlan;
902 else
903 tp->cp_cmd &= ~RxVlan;
904 RTL_W16(CPlusCmd, tp->cp_cmd);
905 RTL_R16(CPlusCmd);
906 spin_unlock_irqrestore(&tp->lock, flags);
907 }
908
909 static void rtl8169_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid)
910 {
911 struct rtl8169_private *tp = netdev_priv(dev);
912 unsigned long flags;
913
914 spin_lock_irqsave(&tp->lock, flags);
915 if (tp->vlgrp)
916 tp->vlgrp->vlan_devices[vid] = NULL;
917 spin_unlock_irqrestore(&tp->lock, flags);
918 }
919
920 static int rtl8169_rx_vlan_skb(struct rtl8169_private *tp, struct RxDesc *desc,
921 struct sk_buff *skb)
922 {
923 u32 opts2 = le32_to_cpu(desc->opts2);
924 int ret;
925
926 if (tp->vlgrp && (opts2 & RxVlanTag)) {
927 rtl8169_rx_hwaccel_skb(skb, tp->vlgrp,
928 swab16(opts2 & 0xffff));
929 ret = 0;
930 } else
931 ret = -1;
932 desc->opts2 = 0;
933 return ret;
934 }
935
936 #else /* !CONFIG_R8169_VLAN */
937
938 static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
939 struct sk_buff *skb)
940 {
941 return 0;
942 }
943
944 static int rtl8169_rx_vlan_skb(struct rtl8169_private *tp, struct RxDesc *desc,
945 struct sk_buff *skb)
946 {
947 return -1;
948 }
949
950 #endif
951
952 static void rtl8169_gset_tbi(struct net_device *dev, struct ethtool_cmd *cmd)
953 {
954 struct rtl8169_private *tp = netdev_priv(dev);
955 void __iomem *ioaddr = tp->mmio_addr;
956 u32 status;
957
958 cmd->supported =
959 SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE;
960 cmd->port = PORT_FIBRE;
961 cmd->transceiver = XCVR_INTERNAL;
962
963 status = RTL_R32(TBICSR);
964 cmd->advertising = (status & TBINwEnable) ? ADVERTISED_Autoneg : 0;
965 cmd->autoneg = !!(status & TBINwEnable);
966
967 cmd->speed = SPEED_1000;
968 cmd->duplex = DUPLEX_FULL; /* Always set */
969 }
970
971 static void rtl8169_gset_xmii(struct net_device *dev, struct ethtool_cmd *cmd)
972 {
973 struct rtl8169_private *tp = netdev_priv(dev);
974 void __iomem *ioaddr = tp->mmio_addr;
975 u8 status;
976
977 cmd->supported = SUPPORTED_10baseT_Half |
978 SUPPORTED_10baseT_Full |
979 SUPPORTED_100baseT_Half |
980 SUPPORTED_100baseT_Full |
981 SUPPORTED_1000baseT_Full |
982 SUPPORTED_Autoneg |
983 SUPPORTED_TP;
984
985 cmd->autoneg = 1;
986 cmd->advertising = ADVERTISED_TP | ADVERTISED_Autoneg;
987
988 if (tp->phy_auto_nego_reg & ADVERTISE_10HALF)
989 cmd->advertising |= ADVERTISED_10baseT_Half;
990 if (tp->phy_auto_nego_reg & ADVERTISE_10FULL)
991 cmd->advertising |= ADVERTISED_10baseT_Full;
992 if (tp->phy_auto_nego_reg & ADVERTISE_100HALF)
993 cmd->advertising |= ADVERTISED_100baseT_Half;
994 if (tp->phy_auto_nego_reg & ADVERTISE_100FULL)
995 cmd->advertising |= ADVERTISED_100baseT_Full;
996 if (tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL)
997 cmd->advertising |= ADVERTISED_1000baseT_Full;
998
999 status = RTL_R8(PHYstatus);
1000
1001 if (status & _1000bpsF)
1002 cmd->speed = SPEED_1000;
1003 else if (status & _100bps)
1004 cmd->speed = SPEED_100;
1005 else if (status & _10bps)
1006 cmd->speed = SPEED_10;
1007
1008 if (status & TxFlowCtrl)
1009 cmd->advertising |= ADVERTISED_Asym_Pause;
1010 if (status & RxFlowCtrl)
1011 cmd->advertising |= ADVERTISED_Pause;