1 /*
2 * r8169.c: RealTek 8169/8168/8101 ethernet driver.
3 *
4 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
5 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
6 * Copyright (c) a lot of people too. Please respect their work.
7 *
8 * See MAINTAINERS file for support contact information.
9 */
10
11 #include "r8169_compat.h"
12 #include <linux/module.h>
13 #include <linux/moduleparam.h>
14 #include <linux/pci.h>
15 #include <linux/netdevice.h>
16 #include <linux/etherdevice.h>
17 #include <linux/delay.h>
18 #include <linux/ethtool.h>
19 #include <linux/mii.h>
20 #include <linux/if_vlan.h>
21 #include <linux/crc32.h>
22 #include <linux/in.h>
23 #include <linux/ip.h>
24 #include <linux/tcp.h>
25 #include <linux/init.h>
26 #include <linux/dma-mapping.h>
27
28 #include <asm/system.h>
29 #include <asm/io.h>
30 #include <asm/irq.h>
31
32 #define RTL8169_VERSION "2.3LK-NAPI"
33 #define MODULENAME "r8169"
34 #define PFX MODULENAME ": "
35
36 #ifdef RTL8169_DEBUG
37 #define assert(expr) \
38 if (!(expr)) { \
39 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
40 #expr,__FILE__,__FUNCTION__,__LINE__); \
41 }
42 #define dprintk(fmt, args...) \
43 do { printk(KERN_DEBUG PFX fmt, ## args); } while (0)
44 #else
45 #define assert(expr) do {} while (0)
46 #define dprintk(fmt, args...) do {} while (0)
47 #endif /* RTL8169_DEBUG */
48
49 #define R8169_MSG_DEFAULT \
50 (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
51
52 #define TX_BUFFS_AVAIL(tp) \
53 (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx - 1)
54
55 /* Maximum events (Rx packets, etc.) to handle at each interrupt. */
56 static const int max_interrupt_work = 20;
57
58 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
59 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
60 static const int multicast_filter_limit = 32;
61
62 /* MAC address length */
63 #define MAC_ADDR_LEN 6
64
65 #define MAX_READ_REQUEST_SHIFT 12
66 #define RX_FIFO_THRESH 7 /* 7 means NO threshold, Rx buffer level before first PCI xfer. */
67 #define RX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
68 #define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
69 #define EarlyTxThld 0x3F /* 0x3F means NO early transmit */
70 #define RxPacketMaxSize 0x3FE8 /* 16K - 1 - ETH_HLEN - VLAN - CRC... */
71 #define SafeMtu 0x1c20 /* ... actually life sucks beyond ~7k */
72 #define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
73
74 #define R8169_REGS_SIZE 256
75 #define R8169_NAPI_WEIGHT 64
76 #define NUM_TX_DESC 64 /* Number of Tx descriptor registers */
77 #define NUM_RX_DESC 256 /* Number of Rx descriptor registers */
78 #define RX_BUF_SIZE 1536 /* Rx Buffer size */
79 #define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc))
80 #define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc))
81
82 #define RTL8169_TX_TIMEOUT (6*HZ)
83 #define RTL8169_PHY_TIMEOUT (10*HZ)
84
85 /* write/read MMIO register */
86 #define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg))
87 #define RTL_W16(reg, val16) writew ((val16), ioaddr + (reg))
88 #define RTL_W32(reg, val32) writel ((val32), ioaddr + (reg))
89 #define RTL_R8(reg) readb (ioaddr + (reg))
90 #define RTL_R16(reg) readw (ioaddr + (reg))
91 #define RTL_R32(reg) ((unsigned long) readl (ioaddr + (reg)))
92
93 enum mac_version {
94 RTL_GIGA_MAC_VER_01 = 0x01, // 8169
95 RTL_GIGA_MAC_VER_02 = 0x02, // 8169S
96 RTL_GIGA_MAC_VER_03 = 0x03, // 8110S
97 RTL_GIGA_MAC_VER_04 = 0x04, // 8169SB
98 RTL_GIGA_MAC_VER_05 = 0x05, // 8110SCd
99 RTL_GIGA_MAC_VER_06 = 0x06, // 8110SCe
100 RTL_GIGA_MAC_VER_07 = 0x07, // 8102e
101 RTL_GIGA_MAC_VER_08 = 0x08, // 8102e
102 RTL_GIGA_MAC_VER_09 = 0x09, // 8102e
103 RTL_GIGA_MAC_VER_10 = 0x0a, // 8101e
104 RTL_GIGA_MAC_VER_11 = 0x0b, // 8168Bb
105 RTL_GIGA_MAC_VER_12 = 0x0c, // 8168Be
106 RTL_GIGA_MAC_VER_13 = 0x0d, // 8101Eb
107 RTL_GIGA_MAC_VER_14 = 0x0e, // 8101 ?
108 RTL_GIGA_MAC_VER_15 = 0x0f, // 8101 ?
109 RTL_GIGA_MAC_VER_16 = 0x11, // 8101Ec
110 RTL_GIGA_MAC_VER_17 = 0x10, // 8168Bf
111 RTL_GIGA_MAC_VER_18 = 0x12, // 8168CP
112 RTL_GIGA_MAC_VER_19 = 0x13, // 8168C
113 RTL_GIGA_MAC_VER_20 = 0x14, // 8168C
114 RTL_GIGA_MAC_VER_21 = 0x15, // 8168C
115 RTL_GIGA_MAC_VER_22 = 0x16, // 8168C
116 RTL_GIGA_MAC_VER_23 = 0x17, // 8168CP
117 RTL_GIGA_MAC_VER_24 = 0x18, // 8168CP
118 RTL_GIGA_MAC_VER_25 = 0x19 // 8168D
119 };
120
121 #define _R(NAME,MAC,MASK) \
122 { .name = NAME, .mac_version = MAC, .RxConfigMask = MASK }
123
124 static const struct {
125 const char *name;
126 u8 mac_version;
127 u32 RxConfigMask; /* Clears the bits supported by this chip */
128 } rtl_chip_info[] = {
129 _R("RTL8169", RTL_GIGA_MAC_VER_01, 0xff7e1880), // 8169
130 _R("RTL8169s", RTL_GIGA_MAC_VER_02, 0xff7e1880), // 8169S
131 _R("RTL8110s", RTL_GIGA_MAC_VER_03, 0xff7e1880), // 8110S
132 _R("RTL8169sb/8110sb", RTL_GIGA_MAC_VER_04, 0xff7e1880), // 8169SB
133 _R("RTL8169sc/8110sc", RTL_GIGA_MAC_VER_05, 0xff7e1880), // 8110SCd
134 _R("RTL8169sc/8110sc", RTL_GIGA_MAC_VER_06, 0xff7e1880), // 8110SCe
135 _R("RTL8102e", RTL_GIGA_MAC_VER_07, 0xff7e1880), // PCI-E
136 _R("RTL8102e", RTL_GIGA_MAC_VER_08, 0xff7e1880), // PCI-E
137 _R("RTL8102e", RTL_GIGA_MAC_VER_09, 0xff7e1880), // PCI-E
138 _R("RTL8101e", RTL_GIGA_MAC_VER_10, 0xff7e1880), // PCI-E
139 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_11, 0xff7e1880), // PCI-E
140 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_12, 0xff7e1880), // PCI-E
141 _R("RTL8101e", RTL_GIGA_MAC_VER_13, 0xff7e1880), // PCI-E 8139
142 _R("RTL8100e", RTL_GIGA_MAC_VER_14, 0xff7e1880), // PCI-E 8139
143 _R("RTL8100e", RTL_GIGA_MAC_VER_15, 0xff7e1880), // PCI-E 8139
144 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_17, 0xff7e1880), // PCI-E
145 _R("RTL8101e", RTL_GIGA_MAC_VER_16, 0xff7e1880), // PCI-E
146 _R("RTL8168cp/8111cp", RTL_GIGA_MAC_VER_18, 0xff7e1880), // PCI-E
147 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_19, 0xff7e1880), // PCI-E
148 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_20, 0xff7e1880), // PCI-E
149 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_21, 0xff7e1880), // PCI-E
150 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_22, 0xff7e1880), // PCI-E
151 _R("RTL8168cp/8111cp", RTL_GIGA_MAC_VER_23, 0xff7e1880), // PCI-E
152 _R("RTL8168cp/8111cp", RTL_GIGA_MAC_VER_24, 0xff7e1880), // PCI-E
153 _R("RTL8168d/8111d", RTL_GIGA_MAC_VER_25, 0xff7e1880) // PCI-E
154 };
155 #undef _R
156
157 enum cfg_version {
158 RTL_CFG_0 = 0x00,
159 RTL_CFG_1,
160 RTL_CFG_2
161 };
162
163 static void rtl_hw_start_8169(struct net_device *);
164 static void rtl_hw_start_8168(struct net_device *);
165 static void rtl_hw_start_8101(struct net_device *);
166
167 static struct pci_device_id rtl8169_pci_tbl[] = {
168 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8129), 0, 0, RTL_CFG_0 },
169 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8136), 0, 0, RTL_CFG_2 },
170 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8167), 0, 0, RTL_CFG_0 },
171 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8168), 0, 0, RTL_CFG_1 },
172 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8169), 0, 0, RTL_CFG_0 },
173 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4300), 0, 0, RTL_CFG_0 },
174 { PCI_DEVICE(PCI_VENDOR_ID_AT, 0xc107), 0, 0, RTL_CFG_0 },
175 { PCI_DEVICE(0x16ec, 0x0116), 0, 0, RTL_CFG_0 },
176 { PCI_VENDOR_ID_LINKSYS, 0x1032,
177 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
178 { 0x0001, 0x8168,
179 PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 },
180 {0,},
181 };
182
183 MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
184
185 static int rx_copybreak = 200;
186 static int use_dac;
187 static struct {
188 u32 msg_enable;
189 } debug = { -1 };
190
191 enum rtl_registers {
192 MAC0 = 0, /* Ethernet hardware address. */
193 MAC4 = 4,
194 MAR0 = 8, /* Multicast filter. */
195 CounterAddrLow = 0x10,
196 CounterAddrHigh = 0x14,
197 TxDescStartAddrLow = 0x20,
198 TxDescStartAddrHigh = 0x24,
199 TxHDescStartAddrLow = 0x28,
200 TxHDescStartAddrHigh = 0x2c,
201 FLASH = 0x30,
202 ERSR = 0x36,
203 ChipCmd = 0x37,
204 TxPoll = 0x38,
205 IntrMask = 0x3c,
206 IntrStatus = 0x3e,
207 TxConfig = 0x40,
208 RxConfig = 0x44,
209 RxMissed = 0x4c,
210 Cfg9346 = 0x50,
211 Config0 = 0x51,
212 Config1 = 0x52,
213 Config2 = 0x53,
214 Config3 = 0x54,
215 Config4 = 0x55,
216 Config5 = 0x56,
217 MultiIntr = 0x5c,
218 PHYAR = 0x60,
219 PHYstatus = 0x6c,
220 RxMaxSize = 0xda,
221 CPlusCmd = 0xe0,
222 IntrMitigate = 0xe2,
223 RxDescAddrLow = 0xe4,
224 RxDescAddrHigh = 0xe8,
225 EarlyTxThres = 0xec,
226 FuncEvent = 0xf0,
227 FuncEventMask = 0xf4,
228 FuncPresetState = 0xf8,
229 FuncForceEvent = 0xfc,
230 };
231
232 enum rtl8110_registers {
233 TBICSR = 0x64,
234 TBI_ANAR = 0x68,
235 TBI_LPAR = 0x6a,
236 };
237
238 enum rtl8168_8101_registers {
239 CSIDR = 0x64,
240 CSIAR = 0x68,
241 #define CSIAR_FLAG 0x80000000
242 #define CSIAR_WRITE_CMD 0x80000000
243 #define CSIAR_BYTE_ENABLE 0x0f
244 #define CSIAR_BYTE_ENABLE_SHIFT 12
245 #define CSIAR_ADDR_MASK 0x0fff
246
247 EPHYAR = 0x80,
248 #define EPHYAR_FLAG 0x80000000
249 #define EPHYAR_WRITE_CMD 0x80000000
250 #define EPHYAR_REG_MASK 0x1f
251 #define EPHYAR_REG_SHIFT 16
252 #define EPHYAR_DATA_MASK 0xffff
253 DBG_REG = 0xd1,
254 #define FIX_NAK_1 (1 << 4)
255 #define FIX_NAK_2 (1 << 3)
256 };
257
258 enum rtl_register_content {
259 /* InterruptStatusBits */
260 SYSErr = 0x8000,
261 PCSTimeout = 0x4000,
262 SWInt = 0x0100,
263 TxDescUnavail = 0x0080,
264 RxFIFOOver = 0x0040,
265 LinkChg = 0x0020,
266 RxOverflow = 0x0010,
267 TxErr = 0x0008,
268 TxOK = 0x0004,
269 RxErr = 0x0002,
270 RxOK = 0x0001,
271
272 /* RxStatusDesc */
273 RxFOVF = (1 << 23),
274 RxRWT = (1 << 22),
275 RxRES = (1 << 21),
276 RxRUNT = (1 << 20),
277 RxCRC = (1 << 19),
278
279 /* ChipCmdBits */
280 CmdReset = 0x10,
281 CmdRxEnb = 0x08,
282 CmdTxEnb = 0x04,
283 RxBufEmpty = 0x01,
284
285 /* TXPoll register p.5 */
286 HPQ = 0x80, /* Poll cmd on the high prio queue */
287 NPQ = 0x40, /* Poll cmd on the low prio queue */
288 FSWInt = 0x01, /* Forced software interrupt */
289
290 /* Cfg9346Bits */
291 Cfg9346_Lock = 0x00,
292 Cfg9346_Unlock = 0xc0,
293
294 /* rx_mode_bits */
295 AcceptErr = 0x20,
296 AcceptRunt = 0x10,
297 AcceptBroadcast = 0x08,
298 AcceptMulticast = 0x04,
299 AcceptMyPhys = 0x02,
300 AcceptAllPhys = 0x01,
301
302 /* RxConfigBits */
303 RxCfgFIFOShift = 13,
304 RxCfgDMAShift = 8,
305
306 /* TxConfigBits */
307 TxInterFrameGapShift = 24,
308 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
309
310 /* Config1 register p.24 */
311 LEDS1 = (1 << 7),
312 LEDS0 = (1 << 6),
313 MSIEnable = (1 << 5), /* Enable Message Signaled Interrupt */
314 Speed_down = (1 << 4),
315 MEMMAP = (1 << 3),
316 IOMAP = (1 << 2),
317 VPD = (1 << 1),
318 PMEnable = (1 << 0), /* Power Management Enable */
319
320 /* Config2 register p. 25 */
321 PCI_Clock_66MHz = 0x01,
322 PCI_Clock_33MHz = 0x00,
323
324 /* Config3 register p.25 */
325 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */
326 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */
327 Beacon_en = (1 << 0), /* 8168 only. Reserved in the 8168b */
328
329 /* Config5 register p.27 */
330 BWF = (1 << 6), /* Accept Broadcast wakeup frame */
331 MWF = (1 << 5), /* Accept Multicast wakeup frame */
332 UWF = (1 << 4), /* Accept Unicast wakeup frame */
333 LanWake = (1 << 1), /* LanWake enable/disable */
334 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */
335
336 /* TBICSR p.28 */
337 TBIReset = 0x80000000,
338 TBILoopback = 0x40000000,
339 TBINwEnable = 0x20000000,
340 TBINwRestart = 0x10000000,
341 TBILinkOk = 0x02000000,
342 TBINwComplete = 0x01000000,
343
344 /* CPlusCmd p.31 */
345 EnableBist = (1 << 15), // 8168 8101
346 Mac_dbgo_oe = (1 << 14), // 8168 8101
347 Normal_mode = (1 << 13), // unused
348 Force_half_dup = (1 << 12), // 8168 8101
349 Force_rxflow_en = (1 << 11), // 8168 8101
350 Force_txflow_en = (1 << 10), // 8168 8101
351 Cxpl_dbg_sel = (1 << 9), // 8168 8101
352 ASF = (1 << 8), // 8168 8101
353 PktCntrDisable = (1 << 7), // 8168 8101
354 Mac_dbgo_sel = 0x001c, // 8168
355 RxVlan = (1 << 6),
356 RxChkSum = (1 << 5),
357 PCIDAC = (1 << 4),
358 PCIMulRW = (1 << 3),
359 INTT_0 = 0x0000, // 8168
360 INTT_1 = 0x0001, // 8168
361 INTT_2 = 0x0002, // 8168
362 INTT_3 = 0x0003, // 8168
363
364 /* rtl8169_PHYstatus */
365 TBI_Enable = 0x80,
366 TxFlowCtrl = 0x40,
367 RxFlowCtrl = 0x20,
368 _1000bpsF = 0x10,
369 _100bps = 0x08,
370 _10bps = 0x04,
371 LinkStatus = 0x02,
372 FullDup = 0x01,
373
374 /* _TBICSRBit */
375 TBILinkOK = 0x02000000,
376
377 /* DumpCounterCommand */
378 CounterDump = 0x8,
379 };
380
381 enum desc_status_bit {
382 DescOwn = (1 << 31), /* Descriptor is owned by NIC */
383 RingEnd = (1 << 30), /* End of descriptor ring */
384 FirstFrag = (1 << 29), /* First segment of a packet */
385 LastFrag = (1 << 28), /* Final segment of a packet */
386
387 /* Tx private */
388 LargeSend = (1 << 27), /* TCP Large Send Offload (TSO) */
389 MSSShift = 16, /* MSS value position */
390 MSSMask = 0xfff, /* MSS value + LargeSend bit: 12 bits */
391 IPCS = (1 << 18), /* Calculate IP checksum */
392 UDPCS = (1 << 17), /* Calculate UDP/IP checksum */
393 TCPCS = (1 << 16), /* Calculate TCP/IP checksum */
394 TxVlanTag = (1 << 17), /* Add VLAN tag */
395
396 /* Rx private */
397 PID1 = (1 << 18), /* Protocol ID bit 1/2 */
398 PID0 = (1 << 17), /* Protocol ID bit 2/2 */
399
400 #define RxProtoUDP (PID1)
401 #define RxProtoTCP (PID0)
402 #define RxProtoIP (PID1 | PID0)
403 #define RxProtoMask RxProtoIP
404
405 IPFail = (1 << 16), /* IP checksum failed */
406 UDPFail = (1 << 15), /* UDP/IP checksum failed */
407 TCPFail = (1 << 14), /* TCP/IP checksum failed */
408 RxVlanTag = (1 << 16), /* VLAN tag available */
409 };
410
411 #define RsvdMask 0x3fffc000
412
413 struct TxDesc {
414 __le32 opts1;
415 __le32 opts2;
416 __le64 addr;
417 };
418
419 struct RxDesc {
420 __le32 opts1;
421 __le32 opts2;
422 __le64 addr;
423 };
424
425 struct ring_info {
426 struct sk_buff *skb;
427 u32 len;
428 u8 __pad[sizeof(void *) - sizeof(u32)];
429 };
430
431 enum features {
432 RTL_FEATURE_WOL = (1 << 0),
433 RTL_FEATURE_MSI = (1 << 1),
434 RTL_FEATURE_GMII = (1 << 2),
435 };
436
437 struct rtl8169_private {
438 void __iomem *mmio_addr; /* memory map physical address */
439 struct pci_dev *pci_dev; /* Index of PCI device */
440 struct net_device *dev;
441 struct net_device_stats stats;
442 spinlock_t lock; /* spin lock flag */
443 u32 msg_enable;
444 int chipset;
445 int mac_version;
446 u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
447 u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
448 u32 dirty_rx;
449 u32 dirty_tx;
450 struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */
451 struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */
452 dma_addr_t TxPhyAddr;
453 dma_addr_t RxPhyAddr;
454 struct sk_buff *Rx_skbuff[NUM_RX_DESC]; /* Rx data buffers */
455 struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */
456 unsigned align;
457 unsigned rx_buf_sz;
458 struct timer_list timer;
459 u16 cp_cmd;
460 u16 intr_event;
461 u16 napi_event;
462 u16 intr_mask;
463 int phy_auto_nego_reg;
464 int phy_1000_ctrl_reg;
465 #ifdef CONFIG_R8169_VLAN
466 struct vlan_group *vlgrp;
467 #endif
468 int (*set_speed)(struct net_device *, u8 autoneg, u16 speed, u8 duplex);
469 int (*get_settings)(struct net_device *, struct ethtool_cmd *);
470 void (*phy_reset_enable)(void __iomem *);
471 void (*hw_start)(struct net_device *);
472 unsigned int (*phy_reset_pending)(void __iomem *);
473 unsigned int (*link_ok)(void __iomem *);
474 int pcie_cap;
475 struct delayed_work task;
476 unsigned features;
477
478 struct mii_if_info mii;
479 };
480
481 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
482 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
483 module_param(rx_copybreak, int, 0);
484 MODULE_PARM_DESC(rx_copybreak, "Copy breakpoint for copy-only-tiny-frames");
485 module_param(use_dac, int, 0);
486 MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
487 module_param_named(debug, debug.msg_enable, int, 0);
488 MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
489 MODULE_LICENSE("GPL");
490 MODULE_VERSION(RTL8169_VERSION);
491
492 static int rtl8169_open(struct net_device *dev);
493 static int rtl8169_start_xmit(struct sk_buff *skb, struct net_device *dev);
494 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance,
495 struct pt_regs *regs);
496 static int rtl8169_init_ring(struct net_device *dev);
497 static void rtl_hw_start(struct net_device *dev);
498 static int rtl8169_close(struct net_device *dev);
499 static void rtl_set_rx_mode(struct net_device *dev);
500 static void rtl8169_tx_timeout(struct net_device *dev);
501 static struct net_device_stats *rtl8169_get_stats(struct net_device *dev);
502 static int rtl8169_rx_interrupt(struct net_device *, struct rtl8169_private *,
503 void __iomem *);
504 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu);
505 static void rtl8169_down(struct net_device *dev);
506 static void rtl8169_rx_clear(struct rtl8169_private *tp);
507 static int rtl8169_poll(struct net_device *dev, int *budget);
508
509 static const unsigned int rtl8169_rx_config =
510 (RX_FIFO_THRESH << RxCfgFIFOShift) | (RX_DMA_BURST << RxCfgDMAShift);
511
512 static void mdio_write(void __iomem *ioaddr, int reg_addr, int value)
513 {
514 int i;
515
516 RTL_W32(PHYAR, 0x80000000 | (reg_addr & 0x1f) << 16 | (value & 0xffff));
517
518 for (i = 20; i > 0; i--) {
519 /*
520 * Check if the RTL8169 has completed writing to the specified
521 * MII register.
522 */
523 if (!(RTL_R32(PHYAR) & 0x80000000))
524 break;
525 udelay(25);
526 }
527 }
528
529 static int mdio_read(void __iomem *ioaddr, int reg_addr)
530 {
531 int i, value = -1;
532
533 RTL_W32(PHYAR, 0x0 | (reg_addr & 0x1f) << 16);
534
535 for (i = 20; i > 0; i--) {
536 /*
537 * Check if the RTL8169 has completed retrieving data from
538 * the specified MII register.
539 */
540 if (RTL_R32(PHYAR) & 0x80000000) {
541 value = RTL_R32(PHYAR) & 0xffff;
542 break;
543 }
544 udelay(25);
545 }
546 return value;
547 }
548
549 static void mdio_patch(void __iomem *ioaddr, int reg_addr, int value)
550 {
551 mdio_write(ioaddr, reg_addr, mdio_read(ioaddr, reg_addr) | value);
552 }
553
554 static void rtl_mdio_write(struct net_device *dev, int phy_id, int location,
555 int val)
556 {
557 struct rtl8169_private *tp = netdev_priv(dev);
558 void __iomem *ioaddr = tp->mmio_addr;
559
560 mdio_write(ioaddr, location, val);
561 }
562
563 static int rtl_mdio_read(struct net_device *dev, int phy_id, int location)
564 {
565 struct rtl8169_private *tp = netdev_priv(dev);
566 void __iomem *ioaddr = tp->mmio_addr;
567
568 return mdio_read(ioaddr, location);
569 }
570
571 static void rtl_ephy_write(void __iomem *ioaddr, int reg_addr, int value)
572 {
573 unsigned int i;
574
575 RTL_W32(EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
576 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
577
578 for (i = 0; i < 100; i++) {
579 if (!(RTL_R32(EPHYAR) & EPHYAR_FLAG))
580 break;
581 udelay(10);
582 }
583 }
584
585 static u16 rtl_ephy_read(void __iomem *ioaddr, int reg_addr)
586 {
587 u16 value = 0xffff;
588 unsigned int i;
589
590 RTL_W32(EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
591
592 for (i = 0; i < 100; i++) {
593 if (RTL_R32(EPHYAR) & EPHYAR_FLAG) {
594 value = RTL_R32(EPHYAR) & EPHYAR_DATA_MASK;
595 break;
596 }
597 udelay(10);
598 }
599
600 return value;
601 }
602
603 static void rtl_csi_write(void __iomem *ioaddr, int addr, int value)
604 {
605 unsigned int i;
606
607 RTL_W32(CSIDR, value);
608 RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
609 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
610
611 for (i = 0; i < 100; i++) {
612 if (!(RTL_R32(CSIAR) & CSIAR_FLAG))
613 break;
614 udelay(10);
615 }
616 }
617
618 static u32 rtl_csi_read(void __iomem *ioaddr, int addr)
619 {
620 u32 value = ~0x00;
621 unsigned int i;
622
623 RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) |
624 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
625
626 for (i = 0; i < 100; i++) {
627 if (RTL_R32(CSIAR) & CSIAR_FLAG) {
628 value = RTL_R32(CSIDR);
629 break;
630 }
631 udelay(10);
632 }
633
634 return value;
635 }
636
637 static void rtl8169_irq_mask_and_ack(void __iomem *ioaddr)
638 {
639 RTL_W16(IntrMask, 0x0000);
640
641 RTL_W16(IntrStatus, 0xffff);
642 }
643
644 static void rtl8169_asic_down(void __iomem *ioaddr)
645 {
646 RTL_W8(ChipCmd, 0x00);
647 rtl8169_irq_mask_and_ack(ioaddr);
648 RTL_R16(CPlusCmd);
649 }
650
651 static unsigned int rtl8169_tbi_reset_pending(void __iomem *ioaddr)
652 {
653 return RTL_R32(TBICSR) & TBIReset;
654 }
655
656 static unsigned int rtl8169_xmii_reset_pending(void __iomem *ioaddr)
657 {
658 return mdio_read(ioaddr, MII_BMCR) & BMCR_RESET;
659 }
660
661 static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr)
662 {
663 return RTL_R32(TBICSR) & TBILinkOk;
664 }
665
666 static unsigned int rtl8169_xmii_link_ok(void __iomem *ioaddr)
667 {
668 return RTL_R8(PHYstatus) & LinkStatus;
669 }
670
671 static void rtl8169_tbi_reset_enable(void __iomem *ioaddr)
672 {
673 RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset);
674 }
675
676 static void rtl8169_xmii_reset_enable(void __iomem *ioaddr)
677 {
678 unsigned int val;
679
680 val = mdio_read(ioaddr, MII_BMCR) | BMCR_RESET;
681 mdio_write(ioaddr, MII_BMCR, val & 0xffff);
682 }
683
684 static void rtl8169_check_link_status(struct net_device *dev,
685 struct rtl8169_private *tp,
686 void __iomem *ioaddr)
687 {
688 unsigned long flags;
689
690 spin_lock_irqsave(&tp->lock, flags);
691 if (tp->link_ok(ioaddr)) {
692 netif_carrier_on(dev);
693 if (netif_msg_ifup(tp))
694 printk(KERN_INFO PFX "%s: link up\n", dev->name);
695 } else {
696 if (netif_msg_ifdown(tp))
697 printk(KERN_INFO PFX "%s: link down\n", dev->name);
698 netif_carrier_off(dev);
699 }
700 spin_unlock_irqrestore(&tp->lock, flags);
701 }
702
703 static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
704 {
705 struct rtl8169_private *tp = netdev_priv(dev);
706 void __iomem *ioaddr = tp->mmio_addr;
707 u8 options;
708
709 wol->wolopts = 0;
710
711 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
712 wol->supported = WAKE_ANY;
713
714 spin_lock_irq(&tp->lock);
715
716 options = RTL_R8(Config1);
717 if (!(options & PMEnable))
718 goto out_unlock;
719
720 options = RTL_R8(Config3);
721 if (options & LinkUp)
722 wol->wolopts |= WAKE_PHY;
723 if (options & MagicPacket)
724 wol->wolopts |= WAKE_MAGIC;
725
726 options = RTL_R8(Config5);
727 if (options & UWF)
728 wol->wolopts |= WAKE_UCAST;
729 if (options & BWF)
730 wol->wolopts |= WAKE_BCAST;
731 if (options & MWF)
732 wol->wolopts |= WAKE_MCAST;
733
734 out_unlock:
735 spin_unlock_irq(&tp->lock);
736 }
737
738 static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
739 {
740 struct rtl8169_private *tp = netdev_priv(dev);
741 void __iomem *ioaddr = tp->mmio_addr;
742 unsigned int i;
743 static struct {
744 u32 opt;
745 u16 reg;
746 u8 mask;
747 } cfg[] = {
748 { WAKE_ANY, Config1, PMEnable },
749 { WAKE_PHY, Config3, LinkUp },
750 { WAKE_MAGIC, Config3, MagicPacket },
751 { WAKE_UCAST, Config5, UWF },
752 { WAKE_BCAST, Config5, BWF },
753 { WAKE_MCAST, Config5, MWF },
754 { WAKE_ANY, Config5, LanWake }
755 };
756
757 spin_lock_irq(&tp->lock);
758
759 RTL_W8(Cfg9346, Cfg9346_Unlock);
760
761 for (i = 0; i < ARRAY_SIZE(cfg); i++) {
762 u8 options = RTL_R8(cfg[i].reg) & ~cfg[i].mask;
763 if (wol->wolopts & cfg[i].opt)
764 options |= cfg[i].mask;
765 RTL_W8(cfg[i].reg, options);
766 }
767
768 RTL_W8(Cfg9346, Cfg9346_Lock);
769
770 if (wol->wolopts)
771 tp->features |= RTL_FEATURE_WOL;
772 else
773 tp->features &= ~RTL_FEATURE_WOL;
774
775 spin_unlock_irq(&tp->lock);
776
777 return 0;
778 }
779
780 static void rtl8169_get_drvinfo(struct net_device *dev,
781 struct ethtool_drvinfo *info)
782 {
783 struct rtl8169_private *tp = netdev_priv(dev);
784
785 strcpy(info->driver, MODULENAME);
786 strcpy(info->version, RTL8169_VERSION);
787 strcpy(info->bus_info, pci_name(tp->pci_dev));
788 }
789
790 static int rtl8169_get_regs_len(struct net_device *dev)
791 {
792 return R8169_REGS_SIZE;
793 }
794
795 static int rtl8169_set_speed_tbi(struct net_device *dev,
796 u8 autoneg, u16 speed, u8 duplex)
797 {
798 struct rtl8169_private *tp = netdev_priv(dev);
799 void __iomem *ioaddr = tp->mmio_addr;
800 int ret = 0;
801 u32 reg;
802
803 reg = RTL_R32(TBICSR);
804 if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) &&
805 (duplex == DUPLEX_FULL)) {
806 RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart));
807 } else if (autoneg == AUTONEG_ENABLE)
808 RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart);
809 else {
810 if (netif_msg_link(tp)) {
811 printk(KERN_WARNING "%s: "
812 "incorrect speed setting refused in TBI mode\n",
813 dev->name);
814 }
815 ret = -EOPNOTSUPP;
816 }
817
818 return ret;
819 }
820
821 static int rtl8169_set_speed_xmii(struct net_device *dev,
822 u8 autoneg, u16 speed, u8 duplex)
823 {
824 struct rtl8169_private *tp = netdev_priv(dev);
825 void __iomem *ioaddr = tp->mmio_addr;
826 int auto_nego, giga_ctrl;
827
828 auto_nego = mdio_read(ioaddr, MII_ADVERTISE);
829 auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
830 ADVERTISE_100HALF | ADVERTISE_100FULL);
831 giga_ctrl = mdio_read(ioaddr, MII_CTRL1000);
832 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
833
834 if (autoneg == AUTONEG_ENABLE) {
835 auto_nego |= (ADVERTISE_10HALF | ADVERTISE_10FULL |
836 ADVERTISE_100HALF | ADVERTISE_100FULL);
837 giga_ctrl |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
838 } else {
839 if (speed == SPEED_10)
840 auto_nego |= ADVERTISE_10HALF | ADVERTISE_10FULL;
841 else if (speed == SPEED_100)
842 auto_nego |= ADVERTISE_100HALF | ADVERTISE_100FULL;
843 else if (speed == SPEED_1000)
844 giga_ctrl |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
845
846 if (duplex == DUPLEX_HALF)
847 auto_nego &= ~(ADVERTISE_10FULL | ADVERTISE_100FULL);
848
849 if (duplex == DUPLEX_FULL)
850 auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_100HALF);
851
852 /* This tweak comes straight from Realtek's driver. */
853 if ((speed == SPEED_100) && (duplex == DUPLEX_HALF) &&
854 ((tp->mac_version == RTL_GIGA_MAC_VER_13) ||
855 (tp->mac_version == RTL_GIGA_MAC_VER_16))) {
856 auto_nego = ADVERTISE_100HALF | ADVERTISE_CSMA;
857 }
858 }
859
860 /* The 8100e/8101e/8102e do Fast Ethernet only. */
861 if ((tp->mac_version == RTL_GIGA_MAC_VER_07) ||
862 (tp->mac_version == RTL_GIGA_MAC_VER_08) ||
863 (tp->mac_version == RTL_GIGA_MAC_VER_09) ||
864 (tp->mac_version == RTL_GIGA_MAC_VER_10) ||
865 (tp->mac_version == RTL_GIGA_MAC_VER_13) ||
866 (tp->mac_version == RTL_GIGA_MAC_VER_14) ||
867 (tp->mac_version == RTL_GIGA_MAC_VER_15) ||
868 (tp->mac_version == RTL_GIGA_MAC_VER_16)) {
869 if ((giga_ctrl & (ADVERTISE_1000FULL | ADVERTISE_1000HALF)) &&
870 netif_msg_link(tp)) {
871 printk(KERN_INFO "%s: PHY does not support 1000Mbps.\n",
872 dev->name);
873 }
874 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
875 }
876
877 auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
878
879 if ((tp->mac_version == RTL_GIGA_MAC_VER_12) ||
880 (tp->mac_version == RTL_GIGA_MAC_VER_17)) {
881 /* Vendor specific (0x1f) and reserved (0x0e) MII registers. */
882 mdio_write(ioaddr, 0x1f, 0x0000);
883 mdio_write(ioaddr, 0x0e, 0x0000);
884 }
885
886 tp->phy_auto_nego_reg = auto_nego;
887 tp->phy_1000_ctrl_reg = giga_ctrl;
888
889 mdio_write(ioaddr, MII_ADVERTISE, auto_nego);
890 mdio_write(ioaddr, MII_CTRL1000, giga_ctrl);
891 mdio_write(ioaddr, MII_BMCR, BMCR_ANENABLE | BMCR_ANRESTART);
892 return 0;
893 }
894
895 static int rtl8169_set_speed(struct net_device *dev,
896 u8 autoneg, u16 speed, u8 duplex)
897 {
898 struct rtl8169_private *tp = netdev_priv(dev);
899 int ret;
900
901 ret = tp->set_speed(dev, autoneg, speed, duplex);
902
903 if (netif_running(dev) && (tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL))
904 mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT);
905
906 return ret;
907 }
908
909 static int rtl8169_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
910 {
911 struct rtl8169_private *tp = netdev_priv(dev);
912 unsigned long flags;
913 int ret;
914
915 spin_lock_irqsave(&tp->lock, flags);
916 ret = rtl8169_set_speed(dev, cmd->autoneg, cmd->speed, cmd->duplex);
917 spin_unlock_irqrestore(&tp->lock, flags);
918
919 return ret;
920 }
921
922 static u32 rtl8169_get_rx_csum(struct net_device *dev)
923 {
924 struct rtl8169_private *tp = netdev_priv(dev);
925
926 return tp->cp_cmd & RxChkSum;
927 }
928
929 static int rtl8169_set_rx_csum(struct net_device *dev, u32 data)
930 {
931 struct rtl8169_private *tp = netdev_priv(dev);
932 void __iomem *ioaddr = tp->mmio_addr;
933 unsigned long flags;
934
935 spin_lock_irqsave(&tp->lock, flags);
936
937 if (data)
938 tp->cp_cmd |= RxChkSum;
939 else
940 tp->cp_cmd &= ~RxChkSum;
941
942 RTL_W16(CPlusCmd, tp->cp_cmd);
943 RTL_R16(CPlusCmd);
944
945 spin_unlock_irqrestore(&tp->lock, flags);
946
947 return 0;
948 }
949
950 #ifdef CONFIG_R8169_VLAN
951
952 static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
953 struct sk_buff *skb)
954 {
955 return (tp->vlgrp && vlan_tx_tag_present(skb)) ?
956 TxVlanTag | swab16(vlan_tx_tag_get(skb)) : 0x00;
957 }
958
959 static void rtl8169_vlan_rx_register(struct net_device *dev,
960 struct vlan_group *grp)
961 {
962 struct rtl8169_private *tp = netdev_priv(dev);
963 void __iomem *ioaddr = tp->mmio_addr;
964 unsigned long flags;
965
966 spin_lock_irqsave(&tp->lock, flags);
967 tp->vlgrp = grp;
968 if (tp->vlgrp)
969 tp->cp_cmd |= RxVlan;
970 else
971 tp->cp_cmd &= ~RxVlan;
972 RTL_W16(CPlusCmd, tp->cp_cmd);
973 RTL_R16(CPlusCmd);
974 spin_unlock_irqrestore(&tp->lock, flags);
975 }
976
977 static void rtl8169_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid)
978 {
979 struct rtl8169_private *tp = netdev_priv(dev);
980 unsigned long flags;
981
982 spin_lock_irqsave(&tp->lock, flags);
983 vlan_group_set_device(tp->vlgrp, vid, NULL);
984 spin_unlock_irqrestore(&tp->lock, flags);
985 }
986
987 static int rtl8169_rx_vlan_skb(struct rtl8169_private *tp, struct RxDesc *desc,
988 struct sk_buff *skb)
989 {
990 u32 opts2 = le32_to_cpu(desc->opts2);
991 struct vlan_group *vlgrp = tp->vlgrp;
992 int ret;
993
994 if (vlgrp && (opts2 & RxVlanTag)) {
995 vlan_hwaccel_receive_skb(skb, vlgrp, swab16(opts2 & 0xffff));
996 ret = 0;
997 } else
998 ret = -1;
999 desc->opts2 = 0;
1000 return ret;
1001 }
1002
1003 #else /* !CONFIG_R8169_VLAN */
1004
1005 static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
1006 struct sk_buff *skb)
1007 {
1008 return 0;
1009 }
1010
1011 static int rtl8169_rx_vlan_skb(struct rtl8169_private *tp, struct RxDesc *desc,
1012 struct sk_buff *skb)
1013 {
1014 return -1;
1015 }
1016
1017 #endif
1018
1019 static int rtl8169_gset_tbi(struct net_device *dev, struct ethtool_cmd *cmd)
1020 {
1021 struct rtl8169_private *tp = netdev_priv(dev);
1022 void __iomem *ioaddr = tp->mmio_addr;
1023 u32 status;
1024
1025 cmd->supported =
1026 SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE;
1027 cmd->port = PORT_FIBRE;
1028 cmd->transceiver = XCVR_INTERNAL;
1029
1030 status = RTL_R32(TBICSR);
1031 cmd->advertising = (status & TBINwEnable) ? ADVERTISED_Autoneg : 0;
1032 cmd->autoneg = !!(status & TBINwEnable);
1033
1034 cmd->speed = SPEED_1000;
1035 cmd->duplex = DUPLEX_FULL; /* Always set */
1036
1037 return 0;
1038 }
1039
1040 static int rtl8169_gset_xmii(struct net_device *dev, struct ethtool_cmd *cmd)
1041 {
1042 struct rtl8169_private *tp = netdev_priv(dev);
1043
1044 return mii_ethtool_gset(&tp->mii, cmd);
1045 }
1046
1047 static int rtl8169_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1048 {
1049 struct rtl8169_private *tp = netdev_priv(dev);
1050 unsigned long flags;
1051 int rc;
1052
1053 spin_lock_irqsave(&tp->lock, flags);
1054
1055 rc = tp->get_settings(dev, cmd);
1056
1057 spin_unlock_irqrestore(&tp->lock, flags);
1058 return rc;
1059 }
1060
1061 static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1062 void *p)
1063 {
1064 struct rtl8169_private *tp = netdev_priv(dev);
1065 unsigned long flags;
1066
1067 if (regs->len > R8169_REGS_SIZE)
1068 regs->len = R8169_REGS_SIZE;
1069
1070 spin_lock_irqsave(&tp->lock, flags);
1071 memcpy_fromio(p, tp->mmio_addr, regs->len);
1072 spin_unlock_irqrestore(&tp->lock, flags);
1073 }
1074
1075 static u32 rtl8169_get_msglevel(struct net_device *dev)
1076 {
1077 struct rtl8169_private *tp = netdev_priv(dev);
1078
1079 return tp->msg_enable;
1080 }
1081
1082 static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
1083 {
1084 struct rtl8169_private *tp = netdev_priv(dev);
1085
1086 tp->msg_enable = value;
1087 }
1088
1089 static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
1090 "tx_packets",
1091 "rx_packets",
1092 "tx_errors",
1093 "rx_errors",
1094 "rx_missed",
1095 "align_errors",
1096 "tx_single_collisions",
1097 "tx_multi_collisions",
1098 "unicast",
1099 "broadcast",
1100 "multicast",
1101 "tx_aborted",
1102 "tx_underrun",
1103 };
1104
1105 struct rtl8169_counters {
1106 __le64 tx_packets;
1107 __le64 rx_packets;
1108 __le64 tx_errors;
1109 __le32 rx_errors;
1110 __le16 rx_missed;
1111 __le16 align_errors;
1112 __le32 tx_one_collision;
1113 __le32 tx_multi_collision;
1114 __le64 rx_unicast;
1115 __le64 rx_broadcast;
1116 __le32 rx_multicast;
1117 __le16 tx_aborted;
1118 __le16 tx_underun;
1119 };
1120
1121 static int rtl8169_get_stats_count(struct net_device *dev)
1122 {
1123 return ARRAY_SIZE(rtl8169_gstrings);
1124 }
1125
1126 static void rtl8169_get_ethtool_stats(struct net_device *dev,
1127 struct ethtool_stats *stats, u64 *data)
1128 {
1129 struct rtl8169_private *tp = netdev_priv(dev);
1130 void __iomem *ioaddr = tp->mmio_addr;
1131 struct rtl8169_counters *counters;
1132 dma_addr_t paddr;
1133 u32 cmd;
1134
1135 ASSERT_RTNL();
1136
1137 counters = pci_alloc_consistent(tp->pci_dev, sizeof(*counters), &paddr);
1138 if (!counters)
1139 return;
1140
1141 RTL_W32(CounterAddrHigh, (u64)paddr >> 32);
1142 cmd = (u64)paddr & DMA_32BIT_MASK;
1143 RTL_W32(CounterAddrLow, cmd);
1144 RTL_W32(CounterAddrLow, cmd | CounterDump);
1145
1146 while (RTL_R32(CounterAddrLow) & CounterDump) {
1147 if (msleep_interruptible(1))
1148 break;
1149 }
1150
1151 RTL_W32(CounterAddrLow, 0);
1152 RTL_W32(CounterAddrHigh, 0);
1153
1154 data[0] = le64_to_cpu(counters->tx_packets);
1155 data[1] = le64_to_cpu(counters->rx_packets);
1156 data[2] = le64_to_cpu(counters->tx_errors);
1157 data[3] = le32_to_cpu(counters->rx_errors);
1158 data[4] = le16_to_cpu(counters->rx_missed);
1159 data[5] = le16_to_cpu(counters->align_errors);
1160 data[6] = le32_to_cpu(counters->tx_one_collision);
1161 data[7] = le32_to_cpu(counters->tx_multi_collision);
1162 data[8] = le64_to_cpu(counters->rx_unicast);
1163 data[9] = le64_to_cpu(counters->rx_broadcast);
1164 data[10] = le32_to_cpu(counters->rx_multicast);
1165 data[11] = le16_to_cpu(counters->tx_aborted);
1166 data[12] = le16_to_cpu(counters->tx_underun);
1167
1168 pci_free_consistent(tp->pci_dev, sizeof(*counters), counters, paddr);
1169 }
1170
1171 static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1172 {
1173 switch(stringset) {
1174 case ETH_SS_STATS:
1175 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
1176 break;
1177 }
1178 }
1179
1180 static const struct ethtool_ops rtl8169_ethtool_ops = {
1181 .get_drvinfo = rtl8169_get_drvinfo,
1182 .get_regs_len = rtl8169_get_regs_len,
1183 .get_link = ethtool_op_get_link,
1184 .get_settings = rtl8169_get_settings,
1185 .set_settings = rtl8169_set_settings,
1186 .get_msglevel = rtl8169_get_msglevel,
1187 .set_msglevel = rtl8169_set_msglevel,
1188 .get_rx_csum = rtl8169_get_rx_csum,
1189 .set_rx_csum = rtl8169_set_rx_csum,
1190 .get_tx_csum = ethtool_op_get_tx_csum,
1191 .set_tx_csum = ethtool_op_set_tx_csum,
1192 .get_sg = ethtool_op_get_sg,
1193 .set_sg = ethtool_op_set_sg,
1194 .get_tso = ethtool_op_get_tso,
1195 .set_tso = ethtool_op_set_tso,
1196 .get_regs = rtl8169_get_regs,
1197 .get_wol = rtl8169_get_wol,
1198 .set_wol = rtl8169_set_wol,
1199 .get_strings = rtl8169_get_strings,
1200 .get_stats_count = rtl8169_get_stats_count,
1201 .get_ethtool_stats = rtl8169_get_ethtool_stats,
1202 .get_perm_addr = ethtool_op_get_perm_addr,
1203 };
1204
1205 static void rtl8169_write_gmii_reg_bit(void __iomem *ioaddr, int reg,
1206 int bitnum, int bitval)
1207 {
1208 int val;
1209
1210 val = mdio_read(ioaddr, reg);
1211 val = (bitval == 1) ?
1212 val | (bitval << bitnum) : val & ~(0x0001 << bitnum);
1213 mdio_write(ioaddr, reg, val & 0xffff);
1214 }
1215
1216 static void rtl8169_get_mac_version(struct rtl8169_private *tp,
1217 void __iomem *ioaddr)
1218 {
1219 /*
1220 * The driver currently handles the 8168Bf and the 8168Be identically
1221 * but they can be identified more specifically through the test below
1222 * if needed:
1223 *
1224 * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
1225 *
1226 * Same thing for the 8101Eb and the 8101Ec:
1227 *
1228 * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
1229 */
1230 const struct {
1231 u32 mask;
1232 u32 val;
1233 int mac_version;
1234 } mac_info[] = {
1235 /* 8168D family. */
1236 { 0x7c800000, 0x28000000, RTL_GIGA_MAC_VER_25 },
1237
1238 /* 8168C family. */
1239 { 0x7cf00000, 0x3ca00000, RTL_GIGA_MAC_VER_24 },
1240 { 0x7cf00000, 0x3c900000, RTL_GIGA_MAC_VER_23 },
1241 { 0x7cf00000, 0x3c800000, RTL_GIGA_MAC_VER_18 },
1242 { 0x7c800000, 0x3c800000, RTL_GIGA_MAC_VER_24 },
1243 { 0x7cf00000, 0x3c000000, RTL_GIGA_MAC_VER_19 },
1244 { 0x7cf00000, 0x3c200000, RTL_GIGA_MAC_VER_20 },
1245 { 0x7cf00000, 0x3c300000, RTL_GIGA_MAC_VER_21 },
1246 { 0x7cf00000, 0x3c400000, RTL_GIGA_MAC_VER_22 },
1247 { 0x7c800000, 0x3c000000, RTL_GIGA_MAC_VER_22 },
1248
1249 /* 8168B family. */
1250 { 0x7cf00000, 0x38000000, RTL_GIGA_MAC_VER_12 },
1251 { 0x7cf00000, 0x38500000, RTL_GIGA_MAC_VER_17 },
1252 { 0x7c800000, 0x38000000, RTL_GIGA_MAC_VER_17 },
1253 { 0x7c800000, 0x30000000, RTL_GIGA_MAC_VER_11 },
1254
1255 /* 8101 family. */
1256 { 0x7cf00000, 0x34a00000, RTL_GIGA_MAC_VER_09 },
1257 { 0x7cf00000, 0x24a00000, RTL_GIGA_MAC_VER_09 },
1258 { 0x7cf00000, 0x34900000, RTL_GIGA_MAC_VER_08 },
1259 { 0x7cf00000, 0x24900000, RTL_GIGA_MAC_VER_08 },
1260 { 0x7cf00000, 0x34800000, RTL_GIGA_MAC_VER_07 },
1261 { 0x7cf00000, 0x24800000, RTL_GIGA_MAC_VER_07 },
1262 { 0x7cf00000, 0x34000000, RTL_GIGA_MAC_VER_13 },
1263 { 0x7cf00000, 0x34300000, RTL_GIGA_MAC_VER_10 },
1264 { 0x7cf00000, 0x34200000, RTL_GIGA_MAC_VER_16 },
1265 { 0x7c800000, 0x34800000, RTL_GIGA_MAC_VER_09 },
1266 { 0x7c800000, 0x24800000, RTL_GIGA_MAC_VER_09 },
1267 { 0x7c800000, 0x34000000, RTL_GIGA_MAC_VER_16 },
1268 /* FIXME: where did these entries come from ? -- FR */
1269 { 0xfc800000, 0x38800000, RTL_GIGA_MAC_VER_15 },
1270 { 0xfc800000, 0x30800000, RTL_GIGA_MAC_VER_14 },
1271
1272 /* 8110 family. */
1273 { 0xfc800000, 0x98000000, RTL_GIGA_MAC_VER_06 },
1274 { 0xfc800000, 0x18000000, RTL_GIGA_MAC_VER_05 },
1275 { 0xfc800000, 0x10000000, RTL_GIGA_MAC_VER_04 },
1276 { 0xfc800000, 0x04000000, RTL_GIGA_MAC_VER_03 },
1277 { 0xfc800000, 0x00800000, RTL_GIGA_MAC_VER_02 },
1278 { 0xfc800000, 0x00000000, RTL_GIGA_MAC_VER_01 },
1279
1280 { 0x00000000, 0x00000000, RTL_GIGA_MAC_VER_01 } /* Catch-all */
1281 }, *p = mac_info;
1282 u32 reg;
1283
1284 reg = RTL_R32(TxConfig);
1285 while ((reg & p->mask) != p->val)
1286 p++;
1287 tp->mac_version = p->mac_version;
1288
1289 if (p->mask == 0x00000000) {
1290 struct pci_dev *pdev = tp->pci_dev;
1291
1292 dev_info(&pdev->dev, "unknown MAC (%08x)\n", reg);
1293 }
1294 }
1295
1296 static void rtl8169_print_mac_version(struct rtl8169_private *tp)
1297 {
1298 dprintk("mac_version = 0x%02x\n", tp->mac_version);
1299 }
1300
1301 struct phy_reg {
1302 u16 reg;
1303 u16 val;
1304 };
1305
1306 static void rtl_phy_write(void __iomem *ioaddr, struct phy_reg *regs, int len)
1307 {
1308 while (len-- > 0) {
1309 mdio_write(ioaddr, regs->reg, regs->val);
1310 regs++;
1311 }
1312 }
1313
1314 static void rtl8169s_hw_phy_config(void __iomem *ioaddr)
1315 {
1316 struct {
1317 u16 regs[5]; /* Beware of bit-sign propagation */
1318 } phy_magic[5] = { {
1319 { 0x0000, //w 4 15 12 0
1320 0x00a1, //w 3 15 0 00a1
1321 0x0008, //w 2 15 0 0008
1322 0x1020, //w 1 15 0 1020
1323 0x1000 } },{ //w 0 15 0 1000
1324 { 0x7000, //w 4 15 12 7
1325 0xff41, //w 3 15 0 ff41
1326 0xde60, //w 2 15 0 de60
1327 0x0140, //w 1 15 0 0140
1328 0x0077 } },{ //w 0 15 0 0077
1329 { 0xa000, //w 4 15 12 a
1330 0xdf01, //w 3 15 0 df01
1331 0xdf20, //w 2 15 0 df20
1332 0xff95, //w 1 15 0 ff95
1333 0xfa00 } },{ //w 0 15 0 fa00
1334 { 0xb000, //w 4 15 12 b
1335 0xff41, //w 3 15 0 ff41
1336 0xde20, //w 2 15 0 de20
1337 0x0140, //w 1 15 0 0140
1338 0x00bb } },{ //w 0 15 0 00bb
1339 { 0xf000, //w 4 15 12 f
1340 0xdf01, //w 3 15 0 df01
1341 0xdf20, //w 2 15 0 df20
1342 0xff95, //w 1 15 0 ff95
1343 0xbf00 } //w 0 15 0 bf00
1344 }
1345 }, *p = phy_magic;
1346 unsigned int i;
1347
1348 mdio_write(ioaddr, 0x1f, 0x0001); //w 31 2 0 1
1349 mdio_write(ioaddr, 0x15, 0x1000); //w 21 15 0 1000
1350 mdio_write(ioaddr, 0x18, 0x65c7); //w 24 15 0 65c7
1351 rtl8169_write_gmii_reg_bit(ioaddr, 4, 11, 0); //w 4 11 11 0
1352
1353 for (i = 0; i < ARRAY_SIZE(phy_magic); i++, p++) {
1354 int val, pos = 4;
1355
1356 val = (mdio_read(ioaddr, pos) & 0x0fff) | (p->regs[0] & 0xffff);
1357 mdio_write(ioaddr, pos, val);
1358 while (--pos >= 0)
1359 mdio_write(ioaddr, pos, p->regs[4 - pos] & 0xffff);
1360 rtl8169_write_gmii_reg_bit(ioaddr, 4, 11, 1); //w 4 11 11 1
1361 rtl8169_write_gmii_reg_bit(ioaddr, 4, 11, 0); //w 4 11 11 0
1362 }
1363 mdio_write(ioaddr, 0x1f, 0x0000); //w 31 2 0 0
1364 }
1365
1366 static void rtl8169sb_hw_phy_config(void __iomem *ioaddr)
1367 {
1368 struct phy_reg phy_reg_init[] = {
1369 { 0x1f, 0x0002 },
1370 { 0x01, 0x90d0 },
1371 { 0x1f, 0x0000 }
1372 };
1373
1374 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1375 }
1376
1377 static void rtl8168bb_hw_phy_config(void __iomem *ioaddr)
1378 {
1379 struct phy_reg phy_reg_init[] = {
1380 { 0x10, 0xf41b },
1381 { 0x1f, 0x0000 }
1382 };
1383
1384 mdio_write(ioaddr, 0x1f, 0x0001);
1385 mdio_patch(ioaddr, 0x16, 1 << 0);
1386
1387 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1388 }
1389
1390 static void rtl8168bef_hw_phy_config(void __iomem *ioaddr)
1391 {
1392 struct phy_reg phy_reg_init[] = {
1393 { 0x1f, 0x0001 },
1394 { 0x10, 0xf41b },
1395 { 0x1f, 0x0000 }
1396 };
1397
1398 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1399 }
1400
1401 static void rtl8168cp_1_hw_phy_config(void __iomem *ioaddr)
1402 {
1403 struct phy_reg phy_reg_init[] = {
1404 { 0x1f, 0x0000 },
1405 { 0x1d, 0x0f00 },
1406 { 0x1f, 0x0002 },
1407 { 0x0c, 0x1ec8 },
1408 { 0x1f, 0x0000 }
1409 };
1410
1411 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1412 }
1413
1414 static void rtl8168cp_2_hw_phy_config(void __iomem *ioaddr)
1415 {
1416 struct phy_reg phy_reg_init[] = {
1417 { 0x1f, 0x0001 },
1418 { 0x1d, 0x3d98 },
1419 { 0x1f, 0x0000 }
1420 };
1421
1422 mdio_write(ioaddr, 0x1f, 0x0000);
1423 mdio_patch(ioaddr, 0x14, 1 << 5);
1424 mdio_patch(ioaddr, 0x0d, 1 << 5);
1425
1426 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1427 }
1428
1429 static void rtl8168c_1_hw_phy_config(void __iomem *ioaddr)
1430 {
1431 struct phy_reg phy_reg_init[] = {
1432 { 0x1f, 0x0001 },
1433 { 0x12, 0x2300 },
1434 { 0x1f, 0x0002 },
1435 { 0x00, 0x88d4 },
1436 { 0x01, 0x82b1 },
1437 { 0x03, 0x7002 },
1438 { 0x08, 0x9e30 },
1439 { 0x09, 0x01f0 },
1440 { 0x0a, 0x5500 },
1441 { 0x0c, 0x00c8 },
1442 { 0x1f, 0x0003 },
1443 { 0x12, 0xc096 },
1444 { 0x16, 0x000a },
1445 { 0x1f, 0x0000 },
1446 { 0x1f, 0x0000 },
1447 { 0x09, 0x2000 },
1448 { 0x09, 0x0000 }
1449 };
1450
1451 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1452
1453 mdio_patch(ioaddr, 0x14, 1 << 5);
1454 mdio_patch(ioaddr, 0x0d, 1 << 5);
1455 mdio_write(ioaddr, 0x1f, 0x0000);
1456 }
1457
1458 static void rtl8168c_2_hw_phy_config(void __iomem *ioaddr)
1459 {
1460 struct phy_reg phy_reg_init[] = {
1461 { 0x1f, 0x0001 },
1462 { 0x12, 0x2300 },
1463 { 0x03, 0x802f },
1464 { 0x02, 0x4f02 },
1465 { 0x01, 0x0409 },
1466 { 0x00, 0xf099 },
1467 { 0x04, 0x9800 },
1468 { 0x04, 0x9000 },
1469 { 0x1d, 0x3d98 },
1470 { 0x1f, 0x0002 },
1471 { 0x0c, 0x7eb8 },
1472 { 0x06, 0x0761 },
1473 { 0x1f, 0x0003 },
1474 { 0x16, 0x0f0a },
1475 { 0x1f, 0x0000 }
1476 };
1477
1478 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1479
1480 mdio_patch(ioaddr, 0x16, 1 << 0);
1481 mdio_patch(ioaddr, 0x14, 1 << 5);
1482 mdio_patch(ioaddr, 0x0d, 1 << 5);
1483 mdio_write(ioaddr, 0x1f, 0x0000);
1484 }
1485
1486 static void rtl8168c_3_hw_phy_config(void __iomem *ioaddr)
1487 {
1488 struct phy_reg phy_reg_init[] = {
1489 { 0x1f, 0x0001 },
1490 { 0x12, 0x2300 },
1491 { 0x1d, 0x3d98 },
1492 { 0x1f, 0x0002 },
1493 { 0x0c, 0x7eb8 },
1494 { 0x06, 0x5461 },
1495 { 0x1f, 0x0003 },
1496 { 0x16, 0x0f0a },
1497 { 0x1f, 0x0000 }
1498 };
1499
1500 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1501
1502 mdio_patch(ioaddr, 0x16, 1 << 0);
1503 mdio_patch(ioaddr, 0x14, 1 << 5);
1504 mdio_patch(ioaddr, 0x0d, 1 << 5);
1505 mdio_write(ioaddr, 0x1f, 0x0000);
1506 }
1507
1508 static void rtl8168c_4_hw_phy_config(void __iomem *ioaddr)
1509 {
1510 rtl8168c_3_hw_phy_config(ioaddr);
1511 }
1512
1513 static void rtl8168d_hw_phy_config(void __iomem *ioaddr)
1514 {
1515 struct phy_reg phy_reg_init_0[] = {
1516 { 0x1f, 0x0001 },
1517 { 0x09, 0x2770 },
1518 { 0x08, 0x04d0 },
1519 { 0x0b, 0xad15 },
1520 { 0x0c, 0x5bf0 },
1521 { 0x1c, 0xf101 },
1522 { 0x1f, 0x0003 },
1523 { 0x14, 0x94d7 },
1524 { 0x12, 0xf4d6 },
1525 { 0x09, 0xca0f },
1526 { 0x1f, 0x0002 },
1527 { 0x0b, 0x0b10 },
1528 { 0x0c, 0xd1f7 },
1529 { 0x1f, 0x0002 },
1530 { 0x06, 0x5461 },
1531 { 0x1f, 0x0002 },
1532 { 0x05, 0x6662 },
1533 { 0x1f, 0x0000 },
1534 { 0x14, 0x0060 },
1535 { 0x1f, 0x0000 },
1536 { 0x0d, 0xf8a0 },
1537 { 0x1f, 0x0005 },
1538 { 0x05, 0xffc2 }
1539 };
1540
1541 rtl_phy_write(ioaddr, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
1542
1543 if (mdio_read(ioaddr, 0x06) == 0xc400) {
1544 struct phy_reg phy_reg_init_1[] = {
1545 { 0x1f, 0x0005 },
1546 { 0x01, 0x0300 },
1547 { 0x1f, 0x0000 },
1548 { 0x11, 0x401c },
1549 { 0x16, 0x4100 },
1550 { 0x1f, 0x0005 },
1551 { 0x07, 0x0010 },
1552 { 0x05, 0x83dc },
1553 { 0x06, 0x087d },
1554 { 0x05, 0x8300 },
1555 { 0x06, 0x0101 },
1556 { 0x06, 0x05f8 },
1557 { 0x06, 0xf9fa },
1558 { 0x06, 0xfbef },
1559 { 0x06, 0x79e2 },
1560 { 0x06, 0x835f },
1561 { 0x06, 0xe0f8 },
1562 { 0x06, 0x9ae1 },
1563 { 0x06, 0xf89b },
1564 { 0x06, 0xef31 },
1565 { 0x06, 0x3b65 },
1566 { 0x06, 0xaa07 },
1567 { 0x06, 0x81e4 },
1568 { 0x06, 0xf89a },
1569 { 0x06, 0xe5f8 },
1570 { 0x06, 0x9baf },
1571 { 0x06, 0x06ae },
1572 { 0x05, 0x83dc },
1573 { 0x06, 0x8300 },
1574 };
1575
1576 rtl_phy_write(ioaddr, phy_reg_init_1,
1577 ARRAY_SIZE(phy_reg_init_1));
1578 }
1579
1580 mdio_write(ioaddr, 0x1f, 0x0000);
1581 }
1582
1583 static void rtl8102e_hw_phy_config(void __iomem *ioaddr)
1584 {
1585 struct phy_reg phy_reg_init[] = {
1586 { 0x1f, 0x0003 },
1587 { 0x08, 0x441d },
1588 { 0x01, 0x9100 },
1589 { 0x1f, 0x0000 }
1590 };
1591
1592 mdio_write(ioaddr, 0x1f, 0x0000);
1593 mdio_patch(ioaddr, 0x11, 1 << 12);
1594 mdio_patch(ioaddr, 0x19, 1 << 13);
1595
1596 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1597 }
1598
1599 static void rtl_hw_phy_config(struct net_device *dev)
1600 {
1601 struct rtl8169_private *tp = netdev_priv(dev);
1602 void __iomem *ioaddr = tp->mmio_addr;
1603
1604 rtl8169_print_mac_version(tp);
1605
1606 switch (tp->mac_version) {
1607 case RTL_GIGA_MAC_VER_01:
1608 break;
1609 case RTL_GIGA_MAC_VER_02:
1610 case RTL_GIGA_MAC_VER_03:
1611 rtl8169s_hw_phy_config(ioaddr);
1612 break;
1613 case RTL_GIGA_MAC_VER_04:
1614 rtl8169sb_hw_phy_config(ioaddr);
1615 break;
1616 case RTL_GIGA_MAC_VER_07:
1617 case RTL_GIGA_MAC_VER_08:
1618 case RTL_GIGA_MAC_VER_09:
1619 rtl8102e_hw_phy_config(ioaddr);
1620 break;
1621 case RTL_GIGA_MAC_VER_11:
1622 rtl8168bb_hw_phy_config(ioaddr);
1623 break;
1624 case RTL_GIGA_MAC_VER_12:
1625 rtl8168bef_hw_phy_config(ioaddr);
1626 break;
1627 case RTL_GIGA_MAC_VER_17:
1628 rtl8168bef_hw_phy_config(ioaddr);
1629 break;
1630 case RTL_GIGA_MAC_VER_18:
1631 rtl8168cp_1_hw_phy_config(ioaddr);
1632 break;
1633 case RTL_GIGA_MAC_VER_19:
1634 rtl8168c_1_hw_phy_config(ioaddr);
1635 break;
1636 case RTL_GIGA_MAC_VER_20:
1637 rtl8168c_2_hw_phy_config(ioaddr);
1638 break;
1639 case RTL_GIGA_MAC_VER_21:
1640 rtl8168c_3_hw_phy_config(ioaddr);
1641 break;
1642 case RTL_GIGA_MAC_VER_22:
1643 rtl8168c_4_hw_phy_config(ioaddr);
1644 break;
1645 case RTL_GIGA_MAC_VER_23:
1646 case RTL_GIGA_MAC_VER_24:
1647 rtl8168cp_2_hw_phy_config(ioaddr);
1648 break;
1649 case RTL_GIGA_MAC_VER_25:
1650 rtl8168d_hw_phy_config(ioaddr);
1651 break;
1652
1653 default:
1654 break;
1655 }
1656 }
1657
1658 static void rtl8169_phy_timer(unsigned long __opaque)
1659 {
1660 struct net_device *dev = (struct net_device *)__opaque;
1661 struct rtl8169_private *tp = netdev_priv(dev);
1662 struct timer_list *timer = &tp->timer;
1663 void __iomem *ioaddr = tp->mmio_addr;
1664 unsigned long timeout = RTL8169_PHY_TIMEOUT;
1665
1666 assert(tp->mac_version > RTL_GIGA_MAC_VER_01);
1667
1668 if (!(tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL))
1669 return;
1670
1671 spin_lock_irq(&tp->lock);
1672
1673 if (tp->phy_reset_pending(ioaddr)) {
1674 /*
1675 * A busy loop could burn quite a few cycles on nowadays CPU.
1676 * Let's delay the execution of the timer for a few ticks.
1677 */
1678 timeout = HZ/10;
1679 goto out_mod_timer;
1680 }
1681
1682 if (tp->link_ok(ioaddr))
1683 goto out_unlock;
1684
1685 if (netif_msg_link(tp))
1686 printk(KERN_WARNING "%s: PHY reset until link up\n", dev->name);
1687
1688 tp->phy_reset_enable(ioaddr);
1689
1690 out_mod_timer:
1691 mod_timer(timer, jiffies + timeout);
1692 out_unlock:
1693 spin_unlock_irq(&tp->lock);
1694 }
1695
1696 static inline void rtl8169_delete_timer(struct net_device *dev)
1697 {
1698 struct rtl8169_private *tp = netdev_priv(dev);
1699 struct timer_list *timer = &tp->timer;
1700
1701 if (tp->mac_version <= RTL_GIGA_MAC_VER_01)
1702 return;
1703
1704 del_timer_sync(timer);
1705 }
1706
1707 static inline void rtl8169_request_timer(struct net_device *dev)
1708 {
1709 struct rtl8169_private *tp = netdev_priv(dev);
1710 struct timer_list *timer = &tp->timer;
1711
1712 if (tp->mac_version <= RTL_GIGA_MAC_VER_01)
1713 return;
1714
1715 mod_timer(timer, jiffies + RTL8169_PHY_TIMEOUT);
1716 }
1717
1718 #ifdef CONFIG_NET_POLL_CONTROLLER
1719 /*
1720 * Polling 'interrupt' - used by things like netconsole to send skbs
1721 * without having to re-enable interrupts. It's not called while
1722 * the interrupt routine is executing.
1723 */
1724 static void rtl8169_netpoll(struct net_device *dev)
1725 {
1726 struct rtl8169_private *tp = netdev_priv(dev);
1727 struct pci_dev *pdev = tp->pci_dev;
1728
1729 disable_irq(pdev->irq);
1730 rtl8169_interrupt(pdev->irq, dev, NULL);
1731 enable_irq(pdev->irq);
1732 }
1733 #endif
1734
1735 static void rtl8169_release_board(struct pci_dev *pdev, struct net_device *dev,
1736 void __iomem *ioaddr)
1737 {
1738 iounmap(ioaddr);
1739 pci_release_regions(pdev);
1740 pci_disable_device(pdev);
1741 free_netdev(dev);
1742 }
1743
1744 static void rtl8169_phy_reset(struct net_device *dev,
1745 struct rtl8169_private *tp)
1746 {
1747 void __iomem *ioaddr = tp->mmio_addr;
1748 unsigned int i;
1749
1750 tp->phy_reset_enable(ioaddr);
1751 for (i = 0; i < 100; i++) {
1752 if (!tp->phy_reset_pending(ioaddr))
1753 return;
1754 msleep(1);
1755 }
1756 if (netif_msg_link(tp))
1757 printk(KERN_ERR "%s: PHY reset failed.\n", dev->name);
1758 }
1759
1760 static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
1761 {
1762 void __iomem *ioaddr = tp->mmio_addr;
1763
1764 rtl_hw_phy_config(dev);
1765
1766 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
1767 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
1768 RTL_W8(0x82, 0x01);
1769 }
1770
1771 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
1772
1773 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
1774 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
1775
1776 if (tp->mac_version == RTL_GIGA_MAC_VER_02) {
1777 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
1778 RTL_W8(0x82, 0x01);
1779 dprintk("Set PHY Reg 0x0bh = 0x00h\n");
1780 mdio_write(ioaddr, 0x0b, 0x0000); //w 0x0b 15 0 0
1781 }
1782
1783 rtl8169_phy_reset(dev, tp);
1784
1785 /*
1786 * rtl8169_set_speed_xmii takes good care of the Fast Ethernet
1787 * only 8101. Don't panic.
1788 */
1789 rtl8169_set_speed(dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL);
1790
1791 if ((RTL_R8(PHYstatus) & TBI_Enable) && netif_msg_link(tp))
1792 printk(KERN_INFO PFX "%s: TBI auto-negotiating\n", dev->name);
1793 }
1794
1795 static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
1796 {
1797 void __iomem *ioaddr = tp->mmio_addr;
1798 u32 high;
1799 u32 low;
1800
1801 low = addr[0] | (addr[1] << 8) | (addr[2] << 16) | (addr[3] << 24);
1802 high = addr[4] | (addr[5] << 8);
1803
1804 spin_lock_irq(&tp->lock);
1805
1806 RTL_W8(Cfg9346, Cfg9346_Unlock);
1807 RTL_W32(MAC0, low);
1808 RTL_W32(MAC4, high);
1809 RTL_W8(Cfg9346, Cfg9346_Lock);
1810
1811 spin_unlock_irq(&tp->lock);
1812 }
1813
1814 static int rtl_set_mac_address(struct net_device *dev, void *p)
1815 {
1816 struct rtl8169_private *tp = netdev_priv(dev);
1817 struct sockaddr *addr = p;
1818
1819 if (!is_valid_ether_addr(addr->sa_data))
1820 return -EADDRNOTAVAIL;
1821
1822 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
1823
1824 rtl_rar_set(tp, dev->dev_addr);
1825
1826 return 0;
1827 }
1828
1829 static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1830 {
1831 struct rtl8169_private *tp = netdev_priv(dev);
1832 struct mii_ioctl_data *data = if_mii(ifr);
1833
1834 if (!netif_running(dev))
1835 return -ENODEV;
1836
1837 switch (cmd) {
1838 case SIOCGMIIPHY:
1839 data->phy_id = 32; /* Internal PHY */
1840 return 0;
1841
1842 case SIOCGMIIREG:
1843 data->val_out = mdio_read(tp->mmio_addr, data->reg_num & 0x1f);
1844 return 0;
1845
1846 case SIOCSMIIREG:
1847 if (!capable(CAP_NET_ADMIN))
1848 return -EPERM;
1849 mdio_write(tp->mmio_addr, data->reg_num & 0x1f, data->val_in);
1850 return 0;
1851 }
1852 return -EOPNOTSUPP;
1853 }
1854
1855 static const struct rtl_cfg_info {
1856 void (*hw_start)(struct net_device *);
1857 unsigned int region;
1858 unsigned int align;
1859 u16 intr_event;
1860 u16 napi_event;
1861 unsigned features;
1862 } rtl_cfg_infos [] = {
1863 [RTL_CFG_0] = {
1864 .hw_start = rtl_hw_start_8169,
1865 .region = 1,
1866 .align = 0,
1867 .intr_event = SYSErr | LinkChg | RxOverflow |
1868 RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
1869 .napi_event = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow,
1870 .features = RTL_FEATURE_GMII
1871 },
1872 [RTL_CFG_1] = {
1873 .hw_start = rtl_hw_start_8168,
1874 .region = 2,
1875 .align = 8,
1876 .intr_event = SYSErr | LinkChg | RxOverflow |
1877 TxErr | TxOK | RxOK | RxErr,
1878 .napi_event = TxErr | TxOK | RxOK | RxOverflow,
1879 .features = RTL_FEATURE_GMII | RTL_FEATURE_MSI
1880 },
1881 [RTL_CFG_2] = {
1882 .hw_start = rtl_hw_start_8101,
1883 .region = 2,
1884 .align = 8,
1885 .intr_event = SYSErr | LinkChg | RxOverflow | PCSTimeout |
1886 RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
1887 .napi_event = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow,
1888 .features = RTL_FEATURE_MSI
1889 }
1890 };
1891
1892 /* Cfg9346_Unlock assumed. */
1893 static unsigned rtl_try_msi(struct pci_dev *pdev, void __iomem *ioaddr,
1894 const struct rtl_cfg_info *cfg)
1895 {
1896 unsigned msi = 0;
1897 u8 cfg2;
1898
1899 cfg2 = RTL_R8(Config2) & ~MSIEnable;
1900 if (cfg->features & RTL_FEATURE_MSI) {
1901 if (pci_enable_msi(pdev)) {
1902 dev_info(&pdev->dev, "no MSI. Back to INTx.\n");
1903 } else {
1904 cfg2 |= MSIEnable;
1905 msi = RTL_FEATURE_MSI;
1906 }
1907 }
1908 RTL_W8(Config2, cfg2);
1909 return msi;
1910 }
1911
1912 static void rtl_disable_msi(struct pci_dev *pdev, struct rtl8169_private *tp)
1913 {
1914 if (tp->features & RTL_FEATURE_MSI) {
1915 pci_disable_msi(pdev);
1916 tp->features &= ~RTL_FEATURE_MSI;
1917 }
1918 }
1919
1920 static int __devinit
1921 rtl8169_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1922 {
1923 const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data;
1924 const unsigned int region = cfg->region;
1925 struct rtl8169_private *tp;
1926 struct mii_if_info *mii;
1927 struct net_device *dev;
1928 void __iomem *ioaddr;
1929 unsigned int i;
1930 int rc;
1931
1932 if (netif_msg_drv(&debug)) {
1933 printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n",
1934 MODULENAME, RTL8169_VERSION);
1935 }
1936
1937 dev = alloc_etherdev(sizeof (*tp));
1938 if (!dev) {
1939 if (netif_msg_drv(&debug))
1940 dev_err(&pdev->dev, "unable to alloc new ethernet\n");
1941 rc = -ENOMEM;
1942 goto out;
1943 }
1944
1945 SET_NETDEV_DEV(dev, &pdev->dev);
1946 tp = netdev_priv(dev);
1947 tp->dev = dev;
1948 tp->pci_dev = pdev;
1949 tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
1950
1951 mii = &tp->mii;
1952 mii->dev = dev;
1953 mii->mdio_read = rtl_mdio_read;
1954 mii->mdio_write = rtl_mdio_write;
1955 mii->phy_id_mask = 0x1f;
1956 mii->reg_num_mask = 0x1f;
1957 mii->supports_gmii = !!(cfg->features & RTL_FEATURE_GMII);
1958
1959 /* enable device (incl. PCI PM wakeup and hotplug setup) */
1960 rc = pci_enable_device(pdev);
1961 if (rc < 0) {
1962 if (netif_msg_probe(tp))
1963 dev_err(&pdev->dev, "enable failure\n");
1964 goto err_out_free_dev_1;
1965 }
1966
1967 rc = pci_set_mwi(pdev);
1968 if (rc < 0)
1969 goto err_out_disable_2;
1970
1971 /* make sure PCI base addr 1 is MMIO */
1972 if (!(pci_resource_flags(pdev, region) & IORESOURCE_MEM)) {
1973 if (netif_msg_probe(tp)) {
1974 dev_err(&pdev->dev,
1975 "region #%d not an MMIO resource, aborting\n",
1976 region);
1977 }
1978 rc = -ENODEV;
1979 goto err_out_mwi_3;
1980 }
1981
1982 /* check for weird/broken PCI region reporting */
1983 if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
1984 if (netif_msg_probe(tp)) {
1985 dev_err(&pdev->dev,
1986 "Invalid PCI region size(s), aborting\n");
1987 }
1988 rc = -ENODEV;
1989 goto err_out_mwi_3;
1990 }
1991
1992 rc = pci_request_regions(pdev, MODULENAME);
1993 if (rc < 0) {
1994 if (netif_msg_probe(tp))
1995 dev_err(&pdev->dev, "could not request regions.\n");
1996 goto err_out_mwi_3;
1997 }
1998
1999 tp->cp_cmd = PCIMulRW | RxChkSum;
2000
2001 if ((sizeof(dma_addr_t) > 4) &&
2002 !pci_set_dma_mask(pdev, DMA_64BIT_MASK) && use_dac) {
2003 tp->cp_cmd |= PCIDAC;
2004 dev->features |= NETIF_F_HIGHDMA;
2005 } else {
2006 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
2007 if (rc < 0) {
2008 if (netif_msg_probe(tp)) {
2009 dev_err(&pdev->dev,
2010 "DMA configuration failed.\n");
2011 }
2012 goto err_out_free_res_4;
2013 }
2014 }
2015
2016 pci_set_master(pdev);
2017
2018 /* ioremap MMIO region */
2019 ioaddr = ioremap(pci_resource_start(pdev, region), R8169_REGS_SIZE);
2020 if (!ioaddr) {
2021 if (netif_msg_probe(tp))
2022 dev_err(&pdev->dev, "cannot remap MMIO, aborting\n");
2023 rc = -EIO;
2024 goto err_out_free_res_4;
2025 }
2026
2027 tp->pcie_cap = pci_find_capability(pdev, PCI_CAP_ID_EXP);
2028 if (!tp->pcie_cap && netif_msg_probe(tp))
2029 dev_info(&pdev->dev, "no PCI Express capability\n");
2030
2031 /* Unneeded ? Don't mess with Mrs. Murphy. */
2032 rtl8169_irq_mask_and_ack(ioaddr);
2033
2034 /* Soft reset the chip. */
2035 RTL_W8(ChipCmd, CmdReset);
2036
2037 /* Check that the chip has finished the reset. */
2038 for (i = 0; i < 100; i++) {
2039 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
2040 break;
2041 msleep_interruptible(1);
2042 }
2043
2044 /* Identify chip attached to board */
2045 rtl8169_get_mac_version(tp, ioaddr);
2046
2047 rtl8169_print_mac_version(tp);
2048
2049 for (i = 0; i < ARRAY_SIZE(rtl_chip_info); i++) {
2050 if (tp->mac_version == rtl_chip_info[i].mac_version)
2051 break;
2052 }
2053 if (i == ARRAY_SIZE(rtl_chip_info)) {
2054 /* Unknown chip: assume array element #0, original RTL-8169 */
2055 if (netif_msg_probe(tp)) {
2056 dev_printk(KERN_DEBUG, &pdev->dev,
2057 "unknown chip version, assuming %s\n",
2058 rtl_chip_info[0].name);
2059 }
2060 i = 0;
2061 }
2062 tp->chipset = i;
2063
2064 RTL_W8(Cfg9346, Cfg9346_Unlock);
2065 RTL_W8(Config1, RTL_R8(Config1) | PMEnable);
2066 RTL_W8(Config5, RTL_R8(Config5) & PMEStatus);
2067 tp->features |= rtl_try_msi(pdev, ioaddr, cfg);
2068 RTL_W8(Cfg9346, Cfg9346_Lock);
2069
2070 if ((tp->mac_version <= RTL_GIGA_MAC_VER_06) &&
2071 (RTL_R8(PHYstatus) & TBI_Enable)) {
2072 tp->set_speed = rtl8169_set_speed_tbi;
2073 tp->get_settings = rtl8169_gset_tbi;
2074 tp->phy_reset_enable = rtl8169_tbi_reset_enable;
2075 tp->phy_reset_pending = rtl8169_tbi_reset_pending;
2076 tp->link_ok = rtl8169_tbi_link_ok;
2077
2078 tp->phy_1000_ctrl_reg = ADVERTISE_1000FULL; /* Implied by TBI */
2079 } else {
2080 tp->set_speed = rtl8169_set_speed_xmii;
2081 tp->get_settings = rtl8169_gset_xmii;
2082 tp->phy_reset_enable = rtl8169_xmii_reset_enable;
2083 tp->phy_reset_pending = rtl8169_xmii_reset_pending;
2084 tp->link_ok = rtl8169_xmii_link_ok;
2085
2086 dev->do_ioctl = rtl8169_ioctl;
2087 }
2088
2089 /* Get MAC address. FIXME: read EEPROM */
2090 for (i = 0; i < MAC_ADDR_LEN; i++)
2091 dev->dev_addr[i] = RTL_R8(MAC0 + i);
2092 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
2093
2094 dev->open = rtl8169_open;
2095 dev->hard_start_xmit = rtl8169_start_xmit;
2096 dev->get_stats = rtl8169_get_stats;
2097 SET_ETHTOOL_OPS(dev, &rtl8169_ethtool_ops);
2098 dev->stop = rtl8169_close;
2099 dev->tx_timeout = rtl8169_tx_timeout;
2100 dev->set_multicast_list = rtl_set_rx_mode;
2101 dev->watchdog_timeo = RTL8169_TX_TIMEOUT;
2102 dev->irq = pdev->irq;
2103 dev->base_addr = (unsigned long) ioaddr;
2104 dev->change_mtu = rtl8169_change_mtu;
2105 dev->set_mac_address = rtl_set_mac_address;
2106
2107 dev->poll = rtl8169_poll;
2108 dev->weight = R8169_NAPI_WEIGHT;
2109
2110 #ifdef CONFIG_R8169_VLAN
2111 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
2112 dev->vlan_rx_register = rtl8169_vlan_rx_register;
2113 dev->vlan_rx_kill_vid = rtl8169_vlan_rx_kill_vid;
2114 #endif
2115
2116 #ifdef CONFIG_NET_POLL_CONTROLLER
2117 dev->poll_controller = rtl8169_netpoll;
2118 #endif
2119
2120 tp->intr_mask = 0xffff;
2121 tp->mmio_addr = ioaddr;
2122 tp->align = cfg->align;
2123 tp->hw_start = cfg->hw_start;
2124 tp->intr_event = cfg->intr_event;
2125 tp->napi_event = cfg->napi_event;
2126
2127 init_timer(&tp->timer);
2128 tp->timer.data = (unsigned long) dev;
2129 tp->timer.function = rtl8169_phy_timer;
2130
2131 spin_lock_init(&tp->lock);
2132
2133 rc = register_netdev(dev);
2134 if (rc < 0)
2135 goto err_out_msi_5;
2136
2137 pci_set_drvdata(pdev, dev);
2138
2139 if (netif_msg_probe(tp)) {
2140 u32 xid = RTL_R32(TxConfig) & 0x7cf0f8ff;
2141
2142 printk(KERN_INFO "%s: %s at 0x%lx, "
2143 "%2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x, "
2144 "XID %08x IRQ %d\n",
2145 dev->name,
2146 rtl_chip_info[tp->chipset].name,
2147 dev->base_addr,
2148 dev->dev_addr[0], dev->dev_addr[1],
2149 dev->dev_addr[2], dev->dev_addr[3],
2150 dev->dev_addr[4], dev->dev_addr[5], xid, dev->irq);
2151 }
2152
2153 rtl8169_init_phy(dev, tp);
2154
2155 out:
2156 return rc;
2157
2158 err_out_msi_5:
2159 rtl_disable_msi(pdev, tp);
2160 iounmap(ioaddr);
2161 err_out_free_res_4:
2162 pci_release_regions(pdev);
2163 err_out_mwi_3:
2164 pci_clear_mwi(pdev);
2165 err_out_disable_2:
2166 pci_disable_device(pdev);
2167 err_out_free_dev_1:
2168 free_netdev(dev);
2169 goto out;
2170 }
2171
2172 static void __devexit rtl8169_remove_one(struct pci_dev *pdev)
2173 {
2174 struct net_device *dev = pci_get_drvdata(pdev);
2175 struct rtl8169_private *tp = netdev_priv(dev);
2176
2177 flush_scheduled_work();
2178
2179 unregister_netdev(dev);
2180 rtl_disable_msi(pdev, tp);
2181 rtl8169_release_board(pdev, dev, tp->mmio_addr);
2182 pci_set_drvdata(pdev, NULL);
2183 }
2184
2185 static void rtl8169_set_rxbufsize(struct rtl8169_private *tp,
2186 struct net_device *dev)
2187 {
2188 unsigned int mtu = dev->mtu;
2189
2190 tp->rx_buf_sz = (mtu > RX_BUF_SIZE) ? mtu + ETH_HLEN + 8 : RX_BUF_SIZE;
2191 }
2192
2193 static int rtl8169_open(struct net_device *dev)
2194 {
2195 struct rtl8169_private *tp = netdev_priv(dev);
2196 struct pci_dev *pdev = tp->pci_dev;
2197 int retval = -ENOMEM;
2198
2199
2200 rtl8169_set_rxbufsize(tp, dev);
2201
2202 /*
2203 * Rx and Tx desscriptors needs 256 bytes alignment.
2204 * pci_alloc_consistent provides more.
2205 */
2206 tp->TxDescArray = pci_alloc_consistent(pdev, R8169_TX_RING_BYTES,
2207 &tp->TxPhyAddr);
2208 if (!tp->TxDescArray)
2209 goto out;
2210
2211 tp->RxDescArray = pci_alloc_consistent(pdev, R8169_RX_RING_BYTES,
2212 &tp->RxPhyAddr);
2213 if (!tp->RxDescArray)
2214 goto err_free_tx_0;
2215
2216 retval = rtl8169_init_ring(dev);
2217 if (retval < 0)
2218 goto err_free_rx_1;
2219
2220 INIT_DELAYED_WORK(&tp->task, NULL);
2221
2222 smp_mb();
2223
2224 retval = request_irq(dev->irq, rtl8169_interrupt,
2225 (tp->features & RTL_FEATURE_MSI) ? 0 : IRQF_SHARED,
2226 dev->name, dev);
2227 if (retval < 0)
2228 goto err_release_ring_2;
2229
2230 netif_poll_enable(dev);
2231
2232 rtl_hw_start(dev);
2233
2234 rtl8169_request_timer(dev);
2235
2236 rtl8169_check_link_status(dev, tp, tp->mmio_addr);
2237 out:
2238 return retval;
2239
2240 err_release_ring_2:
2241 rtl8169_rx_clear(tp);
2242 err_free_rx_1:
2243 pci_free_consistent(pdev, R8169_RX_RING_BYTES, tp->RxDescArray,
2244 tp->RxPhyAddr);
2245 err_free_tx_0:
2246 pci_free_consistent(pdev, R8169_TX_RING_BYTES, tp->TxDescArray,
2247 tp->TxPhyAddr);
2248 goto out;
2249 }
2250
2251 static void rtl8169_hw_reset(void __iomem *ioaddr)
2252 {
2253 /* Disable interrupts */
2254 rtl8169_irq_mask_and_ack(ioaddr);
2255
2256 /* Reset the chipset */
2257 RTL_W8(ChipCmd, CmdReset);
2258
2259 /* PCI commit */
2260 RTL_R8(ChipCmd);
2261 }
2262
2263 static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp)
2264 {
2265 void __iomem *ioaddr = tp->mmio_addr;
2266 u32 cfg = rtl8169_rx_config;
2267
2268 cfg |= (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
2269 RTL_W32(RxConfig, cfg);
2270
2271 /* Set DMA burst size and Interframe Gap Time */
2272 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
2273 (InterFrameGap << TxInterFrameGapShift));
2274 }
2275
2276 static void rtl_hw_start(struct net_device *dev)
2277 {
2278 struct rtl8169_private *tp = netdev_priv(dev);
2279 void __iomem *ioaddr = tp->mmio_addr;
2280 unsigned int i;
2281
2282 /* Soft reset the chip. */
2283 RTL_W8(ChipCmd, CmdReset);
2284
2285 /* Check that the chip has finished the reset. */
2286 for (i = 0; i < 100; i++) {
2287 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
2288 break;
2289 msleep_interruptible(1);
2290 }
2291
2292 tp->hw_start(dev);
2293
2294 netif_start_queue(dev);
2295 }
2296
2297
2298 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp,
2299 void __iomem *ioaddr)
2300 {
2301 /*
2302 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
2303 * register to be written before TxDescAddrLow to work.
2304 * Switching from MMIO to I/O access fixes the issue as well.
2305 */
2306 RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
2307 RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_32BIT_MASK);
2308 RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
2309 RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_32BIT_MASK);
2310 }
2311
2312 static u16 rtl_rw_cpluscmd(void __iomem *ioaddr)
2313 {
2314 u16 cmd;
2315
2316 cmd = RTL_R16(CPlusCmd);
2317 RTL_W16(CPlusCmd, cmd);
2318 return cmd;
2319 }
2320
2321 static void rtl_set_rx_max_size(void __iomem *ioaddr)
2322 {
2323 /* Low hurts. Let's disable the filtering. */
2324 RTL_W16(RxMaxSize, 16383);
2325 }
2326
2327 static void rtl8169_set_magic_reg(void __iomem *ioaddr, unsigned mac_version)
2328 {
2329 struct {
2330 u32 mac_version;
2331 u32 clk;
2332 u32 val;
2333 } cfg2_info [] = {
2334 { RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd
2335 { RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff },
2336 { RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe
2337 { RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff }
2338 }, *p = cfg2_info;
2339 unsigned int i;
2340 u32 clk;
2341
2342 clk = RTL_R8(Config2) & PCI_Clock_66MHz;
2343 for (i = 0; i < ARRAY_SIZE(cfg2_info); i++, p++) {
2344 if ((p->mac_version == mac_version) && (p->clk == clk)) {
2345 RTL_W32(0x7c, p->val);
2346 break;
2347 }
2348 }
2349 }
2350
2351 static void rtl_hw_start_8169(struct net_device *dev)
2352 {
2353 struct rtl8169_private *tp = netdev_priv(dev);
2354 void __iomem *ioaddr = tp->mmio_addr;
2355 struct pci_dev *pdev = tp->pci_dev;
2356
2357 if (tp->mac_version == RTL_GIGA_MAC_VER_05) {
2358 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | PCIMulRW);
2359 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08);
2360 }
2361
2362 RTL_W8(Cfg9346, Cfg9346_Unlock);
2363 if ((tp->mac_version == RTL_GIGA_MAC_VER_01) ||
2364 (tp->mac_version == RTL_GIGA_MAC_VER_02) ||
2365 (tp->mac_version == RTL_GIGA_MAC_VER_03) ||
2366 (tp->mac_version == RTL_GIGA_MAC_VER_04))
2367 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
2368
2369 RTL_W8(EarlyTxThres, EarlyTxThld);
2370
2371 rtl_set_rx_max_size(ioaddr);
2372
2373 if ((tp->mac_version == RTL_GIGA_MAC_VER_01) ||
2374 (tp->mac_version == RTL_GIGA_MAC_VER_02) ||
2375 (tp->mac_version == RTL_GIGA_MAC_VER_03) ||
2376 (tp->mac_version == RTL_GIGA_MAC_VER_04))
2377 rtl_set_rx_tx_config_registers(tp);
2378
2379 tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
2380
2381 if ((tp->mac_version == RTL_GIGA_MAC_VER_02) ||
2382 (tp->mac_version == RTL_GIGA_MAC_VER_03)) {
2383 dprintk("Set MAC Reg C+CR Offset 0xE0. "
2384 "Bit-3 and bit-14 MUST be 1\n");
2385 tp->cp_cmd |= (1 << 14);
2386 }
2387
2388 RTL_W16(CPlusCmd, tp->cp_cmd);
2389
2390 rtl8169_set_magic_reg(ioaddr, tp->mac_version);
2391
2392 /*
2393 * Undocumented corner. Supposedly:
2394 * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
2395 */
2396 RTL_W16(IntrMitigate, 0x0000);
2397
2398 rtl_set_rx_tx_desc_registers(tp, ioaddr);
2399
2400 if ((tp->mac_version != RTL_GIGA_MAC_VER_01) &&
2401 (tp->mac_version != RTL_GIGA_MAC_VER_02) &&
2402 (tp->mac_version != RTL_GIGA_MAC_VER_03) &&
2403 (tp->mac_version != RTL_GIGA_MAC_VER_04)) {
2404 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
2405 rtl_set_rx_tx_config_registers(tp);
2406 }
2407
2408 RTL_W8(Cfg9346, Cfg9346_Lock);
2409
2410 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
2411 RTL_R8(IntrMask);
2412
2413 RTL_W32(RxMissed, 0);
2414
2415 rtl_set_rx_mode(dev);
2416
2417 /* no early-rx interrupts */
2418 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
2419
2420 /* Enable all known interrupts by setting the interrupt mask. */
2421 RTL_W16(IntrMask, tp->intr_event);
2422 }
2423
2424 static void rtl_tx_performance_tweak(struct pci_dev *pdev, u16 force)
2425 {
2426 struct net_device *dev = pci_get_drvdata(pdev);
2427 struct rtl8169_private *tp = netdev_priv(dev);
2428 int cap = tp->pcie_cap;
2429
2430 if (cap) {
2431 u16 ctl;
2432
2433 pci_read_config_word(pdev, cap + PCI_EXP_DEVCTL, &ctl);
2434 ctl = (ctl & ~PCI_EXP_DEVCTL_READRQ) | force;
2435 pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL, ctl);
2436 }
2437 }
2438
2439 static void rtl_csi_access_enable(void __iomem *ioaddr)
2440 {
2441 u32 csi;
2442
2443 csi = rtl_csi_read(ioaddr, 0x070c) & 0x00ffffff;
2444 rtl_csi_write(ioaddr, 0x070c, csi | 0x27000000);
2445 }
2446
2447 struct ephy_info {
2448 unsigned int offset;
2449 u16 mask;
2450 u16 bits;
2451 };
2452
2453 static void rtl_ephy_init(void __iomem *ioaddr, struct ephy_info *e, int len)
2454 {
2455 u16 w;
2456
2457 while (len-- > 0) {
2458 w = (rtl_ephy_read(ioaddr, e->offset) & ~e->mask) | e->bits;
2459 rtl_ephy_write(ioaddr, e->offset, w);
2460 e++;
2461 }
2462 }
2463
2464 static void rtl_disable_clock_request(struct pci_dev *pdev)
2465 {
2466 struct net_device *dev = pci_get_drvdata(pdev);
2467 struct rtl8169_private *tp = netdev_priv(dev);
2468 int cap = tp->pcie_cap;
2469
2470 if (cap) {
2471 u16 ctl;
2472
2473 pci_read_config_word(pdev, cap + PCI_EXP_LNKCTL, &ctl);
2474 ctl &= ~PCI_EXP_LNKCTL_CLKREQ_EN;
2475 pci_write_config_word(pdev, cap + PCI_EXP_LNKCTL, ctl);
2476 }
2477 }
2478
2479 #define R8168_CPCMD_QUIRK_MASK (\
2480 EnableBist | \
2481 Mac_dbgo_oe | \
2482 Force_half_dup | \
2483 Force_rxflow_en | \
2484 Force_txflow_en | \
2485 Cxpl_dbg_sel | \
2486 ASF | \
2487 PktCntrDisable | \
2488 Mac_dbgo_sel)
2489
2490 static void rtl_hw_start_8168bb(void __iomem *ioaddr, struct pci_dev *pdev)
2491 {
2492 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
2493
2494 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
2495
2496 rtl_tx_performance_tweak(pdev,
2497 (0x5 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
2498 }
2499
2500 static void rtl_hw_start_8168bef(void __iomem *ioaddr, struct pci_dev *pdev)
2501 {
2502 rtl_hw_start_8168bb(ioaddr, pdev);
2503
2504 RTL_W8(EarlyTxThres, EarlyTxThld);
2505
2506 RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
2507 }
2508
2509 static void __rtl_hw_start_8168cp(void __iomem *ioaddr, struct pci_dev *pdev)
2510 {
2511 RTL_W8(Config1, RTL_R8(Config1) | Speed_down);
2512
2513 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
2514
2515 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
2516
2517 rtl_disable_clock_request(pdev);
2518
2519 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
2520 }
2521
2522 static void rtl_hw_start_8168cp_1(void __iomem *ioaddr, struct pci_dev *pdev)
2523 {
2524 static struct ephy_info e_info_8168cp[] = {
2525 { 0x01, 0, 0x0001 },
2526 { 0x02, 0x0800, 0x1000 },
2527 { 0x03, 0, 0x0042 },
2528 { 0x06, 0x0080, 0x0000 },
2529 { 0x07, 0, 0x2000 }
2530 };
2531
2532 rtl_csi_access_enable(ioaddr);
2533
2534 rtl_ephy_init(ioaddr, e_info_8168cp, ARRAY_SIZE(e_info_8168cp));
2535
2536 __rtl_hw_start_8168cp(ioaddr, pdev);
2537 }
2538
2539 static void rtl_hw_start_8168cp_2(void __iomem *ioaddr, struct pci_dev *pdev)
2540 {
2541 rtl_csi_access_enable(ioaddr);
2542
2543 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
2544
2545 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
2546
2547 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
2548 }
2549
2550 static void rtl_hw_start_8168cp_3(void __iomem *ioaddr, struct pci_dev *pdev)
2551 {
2552 rtl_csi_access_enable(ioaddr);
2553
2554 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
2555
2556 /* Magic. */
2557 RTL_W8(DBG_REG, 0x20);
2558
2559 RTL_W8(EarlyTxThres, EarlyTxThld);
2560
2561 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
2562
2563 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
2564 }
2565
2566 static void rtl_hw_start_8168c_1(void __iomem *ioaddr, struct pci_dev *pdev)
2567 {
2568 static struct ephy_info e_info_8168c_1[] = {
2569 { 0x02, 0x0800, 0x1000 },
2570 { 0x03, 0, 0x0002 },
2571 { 0x06, 0x0080, 0x0000 }
2572 };
2573
2574 rtl_csi_access_enable(ioaddr);
2575
2576 RTL_W8(DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
2577
2578 rtl_ephy_init(ioaddr, e_info_8168c_1, ARRAY_SIZE(e_info_8168c_1));
2579
2580 __rtl_hw_start_8168cp(ioaddr, pdev);
2581 }
2582
2583 static void rtl_hw_start_8168c_2(void __iomem *ioaddr, struct pci_dev *pdev)
2584 {
2585 static struct ephy_info e_info_8168c_2[] = {
2586 { 0x01, 0, 0x0001 },
2587 { 0x03, 0x0400, 0x0220 }
2588 };
2589
2590 rtl_csi_access_enable(ioaddr);
2591
2592 rtl_ephy_init(ioaddr, e_info_8168c_2, ARRAY_SIZE(e_info_8168c_2));
2593
2594 __rtl_hw_start_8168cp(ioaddr, pdev);
2595 }
2596
2597 static void rtl_hw_start_8168c_3(void __iomem *ioaddr, struct pci_dev *pdev)
2598 {
2599 rtl_hw_start_8168c_2(ioaddr, pdev);
2600 }
2601
2602 static void rtl_hw_start_8168c_4(void __iomem *ioaddr, struct pci_dev *pdev)
2603 {
2604 rtl_csi_access_enable(ioaddr);
2605
2606 __rtl_hw_start_8168cp(ioaddr, pdev);
2607 }
2608
2609 static void rtl_hw_start_8168d(void __iomem *ioaddr, struct pci_dev *pdev)
2610 {
2611 rtl_csi_access_enable(ioaddr);
2612
2613 rtl_disable_clock_request(pdev);
2614
2615 RTL_W8(EarlyTxThres, EarlyTxThld);
2616
2617 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
2618
2619 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
2620 }
2621
2622 static void rtl_hw_start_8168(struct net_device *dev)
2623 {
2624 struct rtl8169_private *tp = netdev_priv(dev);
2625 void __iomem *ioaddr = tp->mmio_addr;
2626 struct pci_dev *pdev = tp->pci_dev;
2627
2628 RTL_W8(Cfg9346, Cfg9346_Unlock);
2629
2630 RTL_W8(EarlyTxThres, EarlyTxThld);
2631
2632 rtl_set_rx_max_size(ioaddr);
2633
2634 tp->cp_cmd |= RTL_R16(CPlusCmd) | PktCntrDisable | INTT_1;
2635
2636 RTL_W16(CPlusCmd, tp->cp_cmd);
2637
2638 RTL_W16(IntrMitigate, 0x5151);
2639
2640 /* Work around for RxFIFO overflow. */
2641 if (tp->mac_version == RTL_GIGA_MAC_VER_11) {
2642 tp->intr_event |= RxFIFOOver | PCSTimeout;
2643 tp->intr_event &= ~RxOverflow;
2644 }
2645
2646 rtl_set_rx_tx_desc_registers(tp, ioaddr);
2647
2648 rtl_set_rx_mode(dev);
2649
2650 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
2651 (InterFrameGap << TxInterFrameGapShift));
2652
2653 RTL_W32(RxMissed, 0);
2654
2655 RTL_R8(IntrMask);
2656
2657 switch (tp->mac_version) {
2658 case RTL_GIGA_MAC_VER_11:
2659 rtl_hw_start_8168bb(ioaddr, pdev);
2660 break;
2661
2662 case RTL_GIGA_MAC_VER_12:
2663 case RTL_GIGA_MAC_VER_17:
2664 rtl_hw_start_8168bef(ioaddr, pdev);
2665 break;
2666
2667 case RTL_GIGA_MAC_VER_18:
2668 rtl_hw_start_8168cp_1(ioaddr, pdev);
2669 break;
2670
2671 case RTL_GIGA_MAC_VER_19:
2672 rtl_hw_start_8168c_1(ioaddr, pdev);
2673 break;
2674
2675 case RTL_GIGA_MAC_VER_20:
2676 rtl_hw_start_8168c_2(ioaddr, pdev);
2677 break;
2678
2679 case RTL_GIGA_MAC_VER_21:
2680 rtl_hw_start_8168c_3(ioaddr, pdev);
2681 break;
2682
2683 case RTL_GIGA_MAC_VER_22:
2684 rtl_hw_start_8168c_4(ioaddr, pdev);
2685 break;
2686
2687 case RTL_GIGA_MAC_VER_23:
2688 rtl_hw_start_8168cp_2(ioaddr, pdev);
2689 break;
2690
2691 case RTL_GIGA_MAC_VER_24:
2692 rtl_hw_start_8168cp_3(ioaddr, pdev);
2693 break;
2694
2695 case RTL_GIGA_MAC_VER_25:
2696 rtl_hw_start_8168d(ioaddr, pdev);
2697 break;
2698
2699 default:
2700 printk(KERN_ERR PFX "%s: unknown chipset (mac_version = %d).\n",
2701 dev->name, tp->mac_version);
2702 break;
2703 }
2704
2705 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
2706
2707 RTL_W8(Cfg9346, Cfg9346_Lock);
2708
2709 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
2710
2711 RTL_W16(IntrMask, tp->intr_event);
2712 }
2713
2714 #define R810X_CPCMD_QUIRK_MASK (\
2715 EnableBist | \
2716 Mac_dbgo_oe | \
2717 Force_half_dup | \
2718 Force_half_dup | \
2719 Force_txflow_en | \
2720 Cxpl_dbg_sel | \
2721 ASF | \
2722 PktCntrDisable | \
2723 PCIDAC | \
2724 PCIMulRW)
2725
2726 static void rtl_hw_start_8102e_1(void __iomem *ioaddr, struct pci_dev *pdev)
2727 {
2728 static struct ephy_info e_info_8102e_1[] = {
2729 { 0x01, 0, 0x6e65 },
2730 { 0x02, 0, 0x091f },
2731 { 0x03, 0, 0xc2f9 },
2732 { 0x06, 0, 0xafb5 },
2733 { 0x07, 0, 0x0e00 },
2734 { 0x19, 0, 0xec80 },
2735 { 0x01, 0, 0x2e65 },
2736 { 0x01, 0, 0x6e65 }
2737 };
2738 u8 cfg1;
2739
2740 rtl_csi_access_enable(ioaddr);
2741
2742 RTL_W8(DBG_REG, FIX_NAK_1);
2743
2744 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
2745
2746 RTL_W8(Config1,
2747 LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
2748 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
2749
2750 cfg1 = RTL_R8(Config1);
2751 if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
2752 RTL_W8(Config1, cfg1 & ~LEDS0);
2753
2754 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R810X_CPCMD_QUIRK_MASK);
2755
2756 rtl_ephy_init(ioaddr, e_info_8102e_1, ARRAY_SIZE(e_info_8102e_1));
2757 }
2758
2759 static void rtl_hw_start_8102e_2(void __iomem *ioaddr, struct pci_dev *pdev)
2760 {
2761 rtl_csi_access_enable(ioaddr);
2762
2763 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
2764
2765 RTL_W8(Config1, MEMMAP | IOMAP | VPD | PMEnable);
2766 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
2767
2768 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R810X_CPCMD_QUIRK_MASK);
2769 }
2770
2771 static void rtl_hw_start_8102e_3(void __iomem *ioaddr, struct pci_dev *pdev)
2772 {
2773 rtl_hw_start_8102e_2(ioaddr, pdev);
2774
2775 rtl_ephy_write(ioaddr, 0x03, 0xc2f9);
2776 }
2777
2778 static void rtl_hw_start_8101(struct net_device *dev)
2779 {
2780 struct rtl8169_private *tp = netdev_priv(dev);
2781 void __iomem *ioaddr = tp->mmio_addr;
2782 struct pci_dev *pdev = tp->pci_dev;
2783
2784 if ((tp->mac_version == RTL_GIGA_MAC_VER_13) ||
2785 (tp->mac_version == RTL_GIGA_MAC_VER_16)) {
2786 int cap = tp->pcie_cap;
2787
2788 if (cap) {
2789 pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL,
2790 PCI_EXP_DEVCTL_NOSNOOP_EN);
2791 }
2792 }
2793
2794 switch (tp->mac_version) {
2795 case RTL_GIGA_MAC_VER_07:
2796 rtl_hw_start_8102e_1(ioaddr, pdev);
2797 break;
2798
2799 case RTL_GIGA_MAC_VER_08:
2800 rtl_hw_start_8102e_3(ioaddr, pdev);
2801 break;
2802
2803 case RTL_GIGA_MAC_VER_09:
2804 rtl_hw_start_8102e_2(ioaddr, pdev);
2805 break;
2806 }
2807
2808 RTL_W8(Cfg9346, Cfg9346_Unlock);
2809
2810 RTL_W8(EarlyTxThres, EarlyTxThld);
2811
2812 rtl_set_rx_max_size(ioaddr);
2813
2814 tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
2815
2816 RTL_W16(CPlusCmd, tp->cp_cmd);
2817
2818 RTL_W16(IntrMitigate, 0x0000);
2819
2820 rtl_set_rx_tx_desc_registers(tp, ioaddr);
2821
2822 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
2823 rtl_set_rx_tx_config_registers(tp);
2824
2825 RTL_W8(Cfg9346, Cfg9346_Lock);
2826
2827 RTL_R8(IntrMask);
2828
2829 RTL_W32(RxMissed, 0);
2830
2831 rtl_set_rx_mode(dev);
2832
2833 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
2834
2835 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
2836
2837 RTL_W16(IntrMask, tp->intr_event);
2838 }
2839
2840 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
2841 {
2842 struct rtl8169_private *tp = netdev_priv(dev);
2843 int ret = 0;
2844
2845 if (new_mtu < ETH_ZLEN || new_mtu > SafeMtu)
2846 return -EINVAL;
2847
2848 dev->mtu = new_mtu;
2849
2850 if (!netif_running(dev))
2851 goto out;
2852
2853 rtl8169_down(dev);
2854
2855 rtl8169_set_rxbufsize(tp, dev);
2856
2857 ret = rtl8169_init_ring(dev);
2858 if (ret < 0)
2859 goto out;
2860
2861 netif_poll_enable(dev);
2862
2863 rtl_hw_start(dev);
2864
2865 rtl8169_request_timer(dev);
2866
2867 out:
2868 return ret;
2869 }
2870
2871 static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
2872 {
2873 desc->addr = cpu_to_le64(0x0badbadbadbadbadull);
2874 desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
2875 }
2876
2877 static void rtl8169_free_rx_skb(struct rtl8169_private *tp,
2878 struct sk_buff **sk_buff, struct RxDesc *desc)
2879 {
2880 struct pci_dev *pdev = tp->pci_dev;
2881
2882 pci_unmap_single(pdev, le64_to_cpu(desc->addr), tp->rx_buf_sz,
2883 PCI_DMA_FROMDEVICE);
2884 dev_kfree_skb(*sk_buff);
2885 *sk_buff = NULL;
2886 rtl8169_make_unusable_by_asic(desc);
2887 }
2888
2889 static inline void rtl8169_mark_to_asic(struct RxDesc *desc, u32 rx_buf_sz)
2890 {
2891 u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
2892
2893 desc->opts1 = cpu_to_le32(DescOwn | eor | rx_buf_sz);
2894 }
2895
2896 static inline void rtl8169_map_to_asic(struct RxDesc *desc, dma_addr_t mapping,
2897 u32 rx_buf_sz)
2898 {
2899 desc->addr = cpu_to_le64(mapping);
2900 wmb();
2901 rtl8169_mark_to_asic(desc, rx_buf_sz);
2902 }
2903
2904 static struct sk_buff *rtl8169_alloc_rx_skb(struct pci_dev *pdev,
2905 struct net_device *dev,
2906 struct RxDesc *desc, int rx_buf_sz,
2907 unsigned int align)
2908 {
2909 struct sk_buff *skb;
2910 dma_addr_t mapping;
2911 unsigned int pad;
2912
2913 pad = align ? align : NET_IP_ALIGN;
2914
2915 skb = netdev_alloc_skb(dev, rx_buf_sz + pad);
2916 if (!skb)
2917 goto err_out;
2918
2919 skb_reserve(skb, align ? ((pad - 1) & (unsigned long)skb->data) : pad);
2920
2921 mapping = pci_map_single(pdev, skb->data, rx_buf_sz,
2922 PCI_DMA_FROMDEVICE);
2923
2924 rtl8169_map_to_asic(desc, mapping, rx_buf_sz);
2925 out:
2926 return skb;
2927
2928 err_out:
2929 rtl8169_make_unusable_by_asic(desc);
2930 goto out;
2931 }
2932
2933 static void rtl8169_rx_clear(struct rtl8169_private *tp)
2934 {
2935 unsigned int i;
2936
2937 for (i = 0; i < NUM_RX_DESC; i++) {
2938 if (tp->Rx_skbuff[i]) {
2939 rtl8169_free_rx_skb(tp, tp->Rx_skbuff + i,
2940 tp->RxDescArray + i);
2941 }
2942 }
2943 }
2944
2945 static u32 rtl8169_rx_fill(struct rtl8169_private *tp, struct net_device *dev,
2946 u32 start, u32 end)
2947 {
2948 u32 cur;
2949
2950 for (cur = start; end - cur != 0; cur++) {
2951 struct sk_buff *skb;
2952 unsigned int i = cur % NUM_RX_DESC;
2953
2954 WARN_ON((s32)(end - cur) < 0);
2955
2956 if (tp->Rx_skbuff[i])
2957 continue;
2958
2959 skb = rtl8169_alloc_rx_skb(tp->pci_dev, dev,
2960 tp->RxDescArray + i,
2961 tp->rx_buf_sz, tp->align);
2962 if (!skb)
2963 break;
2964
2965 tp->Rx_skbuff[i] = skb;
2966 }
2967 return cur - start;
2968 }
2969
2970 static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
2971 {
2972 desc->opts1 |= cpu_to_le32(RingEnd);
2973 }
2974
2975 static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
2976 {
2977 tp->dirty_tx = tp->dirty_rx = tp->cur_tx = tp->cur_rx = 0;
2978 }
2979
2980 static int rtl8169_init_ring(struct net_device *dev)
2981 {
2982 struct rtl8169_private *tp = netdev_priv(dev);
2983
2984 rtl8169_init_ring_indexes(tp);
2985
2986 memset(tp->tx_skb, 0x0, NUM_TX_DESC * sizeof(struct ring_info));
2987 memset(tp->Rx_skbuff, 0x0, NUM_RX_DESC * sizeof(struct sk_buff *));
2988
2989 if (rtl8169_rx_fill(tp, dev, 0, NUM_RX_DESC) != NUM_RX_DESC)
2990 goto err_out;
2991
2992 rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
2993
2994 return 0;
2995
2996 err_out:
2997 rtl8169_rx_clear(tp);
2998 return -ENOMEM;
2999 }
3000
3001 static void rtl8169_unmap_tx_skb(struct pci_dev *pdev, struct ring_info *tx_skb,
3002 struct TxDesc *desc)
3003 {
3004 unsigned int len = tx_skb->len;
3005
3006 pci_unmap_single(pdev, le64_to_cpu(desc->addr), len, PCI_DMA_TODEVICE);
3007 desc->opts1 = 0x00;
3008 desc->opts2 = 0x00;
3009 desc->addr = 0x00;
3010 tx_skb->len = 0;
3011 }
3012
3013 static void rtl8169_tx_clear(struct rtl8169_private *tp)
3014 {
3015 unsigned int i;
3016
3017 for (i = tp->dirty_tx; i < tp->dirty_tx + NUM_TX_DESC; i++) {
3018 unsigned int entry = i % NUM_TX_DESC;
3019 struct ring_info *tx_skb = tp->tx_skb + entry;
3020 unsigned int len = tx_skb->len;
3021
3022 if (len) {
3023 struct sk_buff *skb = tx_skb->skb;
3024
3025 rtl8169_unmap_tx_skb(tp->pci_dev, tx_skb,
3026 tp->TxDescArray + entry);
3027 if (skb) {
3028 dev_kfree_skb(skb);
3029 tx_skb->skb = NULL;
3030 }
3031 tp->stats.tx_dropped++;
3032 }
3033 }
3034 tp->cur_tx = tp->dirty_tx = 0;
3035 }
3036
3037 static void rtl8169_schedule_work(struct net_device *dev, work_func_t task)
3038 {
3039 struct rtl8169_private *tp = netdev_priv(dev);
3040
3041 PREPARE_DELAYED_WORK(&tp->task, task);
3042 schedule_delayed_work(&tp->task, 4);
3043 }
3044
3045 static void rtl8169_wait_for_quiescence(struct net_device *dev)
3046 {
3047 struct rtl8169_private *tp = netdev_priv(dev);
3048 void __iomem *ioaddr = tp->mmio_addr;
3049
3050 synchronize_irq(dev->irq);
3051
3052 /* Wait for any pending NAPI task to complete */
3053 netif_poll_disable(dev);
3054
3055 rtl8169_irq_mask_and_ack(ioaddr);
3056
3057 netif_poll_enable(dev);
3058 }
3059
3060 static void rtl8169_reinit_task(struct work_struct *work)
3061 {
3062 struct rtl8169_private *tp =
3063 container_of(work, struct rtl8169_private, task.work);
3064 struct net_device *dev = tp->dev;
3065 int ret;
3066
3067 rtnl_lock();
3068
3069 if (!netif_running(dev))
3070 goto out_unlock;
3071
3072 rtl8169_wait_for_quiescence(dev);
3073 rtl8169_close(dev);
3074
3075 ret = rtl8169_open(dev);
3076 if (unlikely(ret < 0)) {
3077 if (net_ratelimit() && netif_msg_drv(tp)) {
3078 printk(KERN_ERR PFX "%s: reinit failure (status = %d)."
3079 " Rescheduling.\n", dev->name, ret);
3080 }
3081 rtl8169_schedule_work(dev, rtl8169_reinit_task);
3082 }
3083
3084 out_unlock:
3085 rtnl_unlock();
3086 }
3087
3088 static void rtl8169_reset_task(struct work_struct *work)
3089 {
3090 struct rtl8169_private *tp =
3091 container_of(work, struct rtl8169_private, task.work);
3092 struct net_device *dev = tp->dev;
3093
3094 rtnl_lock();
3095
3096 if (!netif_running(dev))
3097 goto out_unlock;
3098
3099 rtl8169_wait_for_quiescence(dev);
3100
3101 rtl8169_rx_interrupt(dev, tp, tp->mmio_addr);
3102 rtl8169_tx_clear(tp);
3103
3104 if (tp->dirty_rx == tp->cur_rx) {
3105 rtl8169_init_ring_indexes(tp);
3106 rtl_hw_start(dev);
3107 netif_wake_queue(dev);
3108 rtl8169_check_link_status(dev, tp, tp->mmio_addr);
3109 } else {
3110 if (net_ratelimit() && netif_msg_intr(tp)) {
3111 printk(KERN_EMERG PFX "%s: Rx buffers shortage\n",
3112 dev->name);
3113 }
3114 rtl8169_schedule_work(dev, rtl8169_reset_task);
3115 }
3116
3117 out_unlock:
3118 rtnl_unlock();
3119 }
3120
3121 static void rtl8169_tx_timeout(struct net_device *dev)
3122 {
3123 struct rtl8169_private *tp = netdev_priv(dev);
3124
3125 rtl8169_hw_reset(tp->mmio_addr);
3126
3127 /* Let's wait a bit while any (async) irq lands on */
3128 rtl8169_schedule_work(dev, rtl8169_reset_task);
3129 }
3130
3131 static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
3132 u32 opts1)
3133 {
3134 struct skb_shared_info *info = skb_shinfo(skb);
3135 unsigned int cur_frag, entry;
3136 struct TxDesc * uninitialized_var(txd);
3137
3138 entry = tp->cur_tx;
3139 for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
3140 skb_frag_t *frag = info->frags + cur_frag;
3141 dma_addr_t mapping;
3142 u32 status, len;
3143 void *addr;
3144
3145 entry = (entry + 1) % NUM_TX_DESC;
3146
3147 txd = tp->TxDescArray + entry;
3148 len = frag->size;
3149 addr = ((void *) page_address(frag->page)) + frag->page_offset;
3150 mapping = pci_map_single(tp->pci_dev, addr, len, PCI_DMA_TODEVICE);
3151
3152 /* anti gcc 2.95.3 bugware (sic) */
3153 status = opts1 | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
3154
3155 txd->opts1 = cpu_to_le32(status);
3156 txd->addr = cpu_to_le64(mapping);
3157
3158 tp->tx_skb[entry].len = len;
3159 }
3160
3161 if (cur_frag) {
3162 tp->tx_skb[entry].skb = skb;
3163 txd->opts1 |= cpu_to_le32(LastFrag);
3164 }
3165
3166 return cur_frag;
3167 }
3168
3169 static inline u32 rtl8169_tso_csum(struct sk_buff *skb, struct net_device *dev)
3170 {
3171 if (dev->features & NETIF_F_TSO) {
3172 u32 mss = skb_shinfo(skb)->gso_size;
3173
3174 if (mss)
3175 return LargeSend | ((mss & MSSMask) << MSSShift);
3176 }
3177 if (skb->ip_summed == CHECKSUM_PARTIAL) {
3178 const struct iphdr *ip = ip_hdr(skb);
3179
3180 if (ip->protocol == IPPROTO_TCP)
3181 return IPCS | TCPCS;
3182 else if (ip->protocol == IPPROTO_UDP)
3183 return IPCS | UDPCS;
3184 WARN_ON(1); /* we need a WARN() */
3185 }
3186 return 0;
3187 }
3188
3189 static int rtl8169_start_xmit(struct sk_buff *skb, struct net_device *dev)
3190 {
3191 struct rtl8169_private *tp = netdev_priv(dev);
3192 unsigned int frags, entry = tp->cur_tx % NUM_TX_DESC;
3193 struct TxDesc *txd = tp->TxDescArray + entry;
3194 void __iomem *ioaddr = tp->mmio_addr;
3195 dma_addr_t mapping;
3196 u32 status, len;
3197 u32 opts1;
3198 int ret = NETDEV_TX_OK;
3199
3200 if (unlikely(TX_BUFFS_AVAIL(tp) < skb_shinfo(skb)->nr_frags)) {
3201 if (netif_msg_drv(tp)) {
3202 printk(KERN_ERR
3203 "%s: BUG! Tx Ring full when queue awake!\n",
3204 dev->name);
3205 }
3206 goto err_stop;
3207 }
3208
3209 if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
3210 goto err_stop;
3211
3212 opts1 = DescOwn | rtl8169_tso_csum(skb, dev);
3213
3214 frags = rtl8169_xmit_frags(tp, skb, opts1);
3215 if (frags) {
3216 len = skb_headlen(skb);
3217 opts1 |= FirstFrag;
3218 } else {
3219 len = skb->len;
3220
3221 if (unlikely(len < ETH_ZLEN)) {
3222 if (skb_padto(skb, ETH_ZLEN))
3223 goto err_update_stats;
3224 len = ETH_ZLEN;
3225 }
3226
3227 opts1 |= FirstFrag | LastFrag;
3228 tp->tx_skb[entry].skb = skb;
3229 }
3230
3231 mapping = pci_map_single(tp->pci_dev, skb->data, len, PCI_DMA_TODEVICE);
3232
3233 tp->tx_skb[entry].len = len;
3234 txd->addr = cpu_to_le64(mapping);
3235 txd->opts2 = cpu_to_le32(rtl8169_tx_vlan_tag(tp, skb));
3236
3237 wmb();
3238
3239 /* anti gcc 2.95.3 bugware (sic) */
3240 status = opts1 | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
3241 txd->opts1 = cpu_to_le32(status);
3242
3243 dev->trans_start = jiffies;
3244
3245 tp->cur_tx += frags + 1;
3246
3247 smp_wmb();
3248
3249 RTL_W8(TxPoll, NPQ); /* set polling bit */
3250
3251 if (TX_BUFFS_AVAIL(tp) < MAX_SKB_FRAGS) {
3252 netif_stop_queue(dev);
3253 smp_rmb();
3254 if (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)
3255 netif_wake_queue(dev);
3256 }
3257
3258 out:
3259 return ret;
3260
3261 err_stop:
3262 netif_stop_queue(dev);
3263 ret = NETDEV_TX_BUSY;
3264 err_update_stats:
3265 tp->stats.tx_dropped++;
3266 goto out;
3267 }
3268
3269 static void rtl8169_pcierr_interrupt(struct net_device *dev)
3270 {
3271 struct rtl8169_private *tp = netdev_priv(dev);
3272 struct pci_dev *pdev = tp->pci_dev;
3273 void __iomem *ioaddr = tp->mmio_addr;
3274 u16 pci_status, pci_cmd;
3275
3276 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
3277 pci_read_config_word(pdev, PCI_STATUS, &pci_status);
3278
3279 if (netif_msg_intr(tp)) {
3280 printk(KERN_ERR
3281 "%s: PCI error (cmd = 0x%04x, status = 0x%04x).\n",
3282 dev->name, pci_cmd, pci_status);
3283 }
3284
3285 /*
3286 * The recovery sequence below admits a very elaborated explanation:
3287 * - it seems to work;
3288 * - I did not see what else could be done;
3289 * - it makes iop3xx happy.
3290 *
3291 * Feel free to adjust to your needs.
3292 */
3293 if (pdev->broken_parity_status)
3294 pci_cmd &= ~PCI_COMMAND_PARITY;
3295 else
3296 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
3297
3298 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
3299
3300 pci_write_config_word(pdev, PCI_STATUS,
3301 pci_status & (PCI_STATUS_DETECTED_PARITY |
3302 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
3303 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
3304
3305 /* The infamous DAC f*ckup only happens at boot time */
3306 if ((tp->cp_cmd & PCIDAC) && !tp->dirty_rx && !tp->cur_rx) {
3307 if (netif_msg_intr(tp))
3308 printk(KERN_INFO "%s: disabling PCI DAC.\n", dev->name);
3309 tp->cp_cmd &= ~PCIDAC;
3310 RTL_W16(CPlusCmd, tp->cp_cmd);
3311 dev->features &= ~NETIF_F_HIGHDMA;
3312 }
3313
3314 rtl8169_hw_reset(ioaddr);
3315
3316 rtl8169_schedule_work(dev, rtl8169_reinit_task);
3317 }
3318
3319 static void rtl8169_tx_interrupt(struct net_device *dev,
3320 struct rtl8169_private *tp,
3321 void __iomem *ioaddr)
3322 {
3323 unsigned int dirty_tx, tx_left;
3324
3325 dirty_tx = tp->dirty_tx;
3326 smp_rmb();
3327 tx_left = tp->cur_tx - dirty_tx;
3328
3329 while (tx_left > 0) {
3330 unsigned int entry = dirty_tx % NUM_TX_DESC;
3331 struct ring_info *tx_skb = tp->tx_skb + entry;
3332 u32 len = tx_skb->len;
3333 u32 status;
3334
3335 rmb();
3336 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
3337 if (status & DescOwn)
3338 break;
3339
3340 tp->stats.tx_bytes += len;
3341 tp->stats.tx_packets++;
3342
3343 rtl8169_unmap_tx_skb(tp->pci_dev, tx_skb, tp->TxDescArray + entry);
3344
3345 if (status & LastFrag) {
3346 dev_kfree_skb_irq(tx_skb->skb);
3347 tx_skb->skb = NULL;
3348 }
3349 dirty_tx++;
3350 tx_left--;
3351 }
3352
3353 if (tp->dirty_tx != dirty_tx) {
3354 tp->dirty_tx = dirty_tx;
3355 smp_wmb();
3356 if (netif_queue_stopped(dev) &&
3357 (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)) {
3358 netif_wake_queue(dev);
3359 }
3360 /*
3361 * 8168 hack: TxPoll requests are lost when the Tx packets are
3362 * too close. Let's kick an extra TxPoll request when a burst
3363 * of start_xmit activity is detected (if it is not detected,
3364 * it is slow enough). -- FR
3365 */
3366 smp_rmb();
3367 if (tp->cur_tx != dirty_tx)
3368 RTL_W8(TxPoll, NPQ);
3369 }
3370 }
3371
3372 static inline int rtl8169_fragmented_frame(u32 status)
3373 {
3374 return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
3375 }
3376
3377 static inline void rtl8169_rx_csum(struct sk_buff *skb, struct RxDesc *desc)
3378 {
3379 u32 opts1 = le32_to_cpu(desc->opts1);
3380 u32 status = opts1 & RxProtoMask;
3381
3382 if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
3383 ((status == RxProtoUDP) && !(opts1 & UDPFail)) ||
3384 ((status == RxProtoIP) && !(opts1 & IPFail)))
3385 skb->ip_summed = CHECKSUM_UNNECESSARY;
3386 else
3387 skb->ip_summed = CHECKSUM_NONE;
3388 }
3389
3390 static inline bool rtl8169_try_rx_copy(struct sk_buff **sk_buff,
3391 struct rtl8169_private *tp, int pkt_size,
3392 dma_addr_t addr)
3393 {
3394 struct sk_buff *skb;
3395 bool done = false;
3396
3397 if (pkt_size >= rx_copybreak)
3398 goto out;
3399
3400 skb = netdev_alloc_skb(tp->dev, pkt_size + NET_IP_ALIGN);
3401 if (!skb)
3402 goto out;
3403
3404 pci_dma_sync_single_for_cpu(tp->pci_dev, addr, pkt_size,
3405 PCI_DMA_FROMDEVICE);
3406 skb_reserve(skb, NET_IP_ALIGN);
3407 skb_copy_from_linear_data(*sk_buff, skb->data, pkt_size);
3408 *sk_buff = skb;
3409 done = true;
3410 out:
3411 return done;
3412 }
3413
3414 static int rtl8169_rx_interrupt(struct net_device *dev,
3415 struct rtl8169_private *tp,
3416 void __iomem *ioaddr)
3417 {
3418 unsigned int cur_rx, rx_left;
3419 unsigned int delta, count;
3420
3421 cur_rx = tp->cur_rx;
3422 rx_left = NUM_RX_DESC + tp->dirty_rx - cur_rx;
3423 rx_left = min(rx_left, (u32) dev->quota);
3424
3425 for (; rx_left > 0; rx_left--, cur_rx++) {
3426 unsigned int entry = cur_rx % NUM_RX_DESC;
3427 struct RxDesc *desc = tp->RxDescArray + entry;
3428 u32 status;
3429
3430 rmb();
3431 status = le32_to_cpu(desc->opts1);
3432
3433 if (status & DescOwn)
3434 break;
3435 if (unlikely(status & RxRES)) {
3436 if (netif_msg_rx_err(tp)) {
3437 printk(KERN_INFO
3438 "%s: Rx ERROR. status = %08x\n",
3439 dev->name, status);
3440 }
3441 tp->stats.rx_errors++;
3442 if (status & (RxRWT | RxRUNT))
3443 tp->stats.rx_length_errors++;
3444 if (status & RxCRC)
3445 tp->stats.rx_crc_errors++;
3446 if (status & RxFOVF) {
3447 rtl8169_schedule_work(dev, rtl8169_reset_task);
3448 tp->stats.rx_fifo_errors++;
3449 }
3450 rtl8169_mark_to_asic(desc, tp->rx_buf_sz);
3451 } else {
3452 struct sk_buff *skb = tp->Rx_skbuff[entry];
3453 dma_addr_t addr = le64_to_cpu(desc->addr);
3454 int pkt_size = (status & 0x00001FFF) - 4;
3455 struct pci_dev *pdev = tp->pci_dev;
3456
3457 /*
3458 * The driver does not support incoming fragmented
3459 * frames. They are seen as a symptom of over-mtu
3460 * sized frames.
3461 */
3462 if (unlikely(rtl8169_fragmented_frame(status))) {
3463 tp->stats.rx_dropped++;
3464 tp->stats.rx_length_errors++;
3465 rtl8169_mark_to_asic(desc, tp->rx_buf_sz);
3466 continue;
3467 }
3468
3469 rtl8169_rx_csum(skb, desc);
3470
3471 if (rtl8169_try_rx_copy(&skb, tp, pkt_size, addr)) {
3472 pci_dma_sync_single_for_device(pdev, addr,
3473 pkt_size, PCI_DMA_FROMDEVICE);
3474 rtl8169_mark_to_asic(desc, tp->rx_buf_sz);
3475 } else {
3476 pci_unmap_single(pdev, addr, pkt_size,
3477 PCI_DMA_FROMDEVICE);
3478 tp->Rx_skbuff[entry] = NULL;
3479 }
3480
3481 skb_put(skb, pkt_size);
3482 skb->protocol = eth_type_trans(skb, dev);
3483
3484 if (rtl8169_rx_vlan_skb(tp, desc, skb) < 0)
3485 netif_receive_skb(skb);
3486
3487 dev->last_rx = jiffies;
3488 tp->stats.rx_bytes += pkt_size;
3489 tp->stats.rx_packets++;
3490 }
3491
3492 /* Work around for AMD plateform. */
3493 if ((desc->opts2 & cpu_to_le32(0xfffe000)) &&
3494 (tp->mac_version == RTL_GIGA_MAC_VER_05)) {
3495 desc->opts2 = 0;
3496 cur_rx++;
3497 }
3498 }
3499
3500 count = cur_rx - tp->cur_rx;
3501 tp->cur_rx = cur_rx;
3502
3503 delta = rtl8169_rx_fill(tp, dev, tp->dirty_rx, tp->cur_rx);
3504 if (!delta && count && netif_msg_intr(tp))
3505 printk(KERN_INFO "%s: no Rx buffer allocated\n", dev->name);
3506 tp->dirty_rx += delta;
3507
3508 /*
3509 * FIXME: until there is periodic timer to try and refill the ring,
3510 * a temporary shortage may definitely kill the Rx process.
3511 * - disable the asic to try and avoid an overflow and kick it again
3512 * after refill ?
3513 * - how do others driver handle this condition (Uh oh...).
3514 */
3515 if ((tp->dirty_rx + NUM_RX_DESC == tp->cur_rx) && netif_msg_intr(tp))
3516 printk(KERN_EMERG "%s: Rx buffers exhausted\n", dev->name);
3517
3518 return count;
3519 }
3520
3521 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance,
3522 struct pt_regs *regs)
3523 {
3524 struct net_device *dev = dev_instance;
3525 struct rtl8169_private *tp = netdev_priv(dev);
3526 void __iomem *ioaddr = tp->mmio_addr;
3527 int handled = 0;
3528 int status;
3529
3530 status = RTL_R16(IntrStatus);
3531
3532 /* hotplug/major error/no more work/shared irq */
3533 if ((status == 0xffff) || !status)
3534 goto out;
3535
3536 handled = 1;
3537
3538 if (unlikely(!netif_running(dev))) {
3539 rtl8169_asic_down(ioaddr);
3540 goto out;
3541 }
3542
3543 status &= tp->intr_mask;
3544 RTL_W16(IntrStatus,
3545 (status & RxFIFOOver) ? (status | RxOverflow) : status);
3546
3547 if (!(status & tp->intr_event))
3548 goto out;
3549
3550 /* Work around for rx fifo overflow */
3551 if (unlikely(status & RxFIFOOver) &&
3552 (tp->mac_version == RTL_GIGA_MAC_VER_11)) {
3553 netif_stop_queue(dev);
3554 rtl8169_tx_timeout(dev);
3555 goto out;
3556 }
3557
3558 if (unlikely(status & SYSErr)) {
3559 rtl8169_pcierr_interrupt(dev);
3560 goto out;
3561 }
3562
3563 if (status & LinkChg)
3564 rtl8169_check_link_status(dev, tp, ioaddr);
3565
3566 if (status & tp->napi_event) {
3567 RTL_W16(IntrMask, tp->intr_event & ~tp->napi_event);
3568 tp->intr_mask = ~tp->napi_event;
3569
3570 if (likely(netif_rx_schedule_prep(dev)))
3571 __netif_rx_schedule(dev);
3572 else if (netif_msg_intr(tp)) {
3573 printk(KERN_INFO "%s: interrupt %04x in poll\n",
3574 dev->name, status);
3575 }
3576 }
3577 out:
3578 return IRQ_RETVAL(handled);
3579 }
3580
3581 static int rtl8169_poll(struct net_device *dev, int *budget)
3582 {
3583 unsigned int work_done, work_to_do = min(*budget, dev->quota);
3584 struct rtl8169_private *tp = netdev_priv(dev);
3585 void __iomem *ioaddr = tp->mmio_addr;
3586
3587 work_done = rtl8169_rx_interrupt(dev, tp, ioaddr);
3588 rtl8169_tx_interrupt(dev, tp, ioaddr);
3589
3590 *budget -= work_done;
3591 dev->quota -= work_done;
3592
3593 if (work_done < work_to_do) {
3594 netif_rx_complete(dev);
3595 tp->intr_mask = 0xffff;
3596 /*
3597 * 20040426: the barrier is not strictly required but the
3598 * behavior of the irq handler could be less predictable
3599 * without it. Btw, the lack of flush for the posted pci
3600 * write is safe - FR
3601 */
3602 smp_wmb();
3603 RTL_W16(IntrMask, tp->intr_event);
3604 }
3605
3606 return (work_done >= work_to_do);
3607 }
3608
3609 static void rtl8169_down(struct net_device *dev)
3610 {
3611 struct rtl8169_private *tp = netdev_priv(dev);
3612 void __iomem *ioaddr = tp->mmio_addr;
3613 unsigned int intrmask;
3614
3615 rtl8169_delete_timer(dev);
3616
3617 netif_stop_queue(dev);
3618
3619 netif_poll_disable(dev);
3620
3621 core_down:
3622 spin_lock_irq(&tp->lock);
3623
3624 rtl8169_asic_down(ioaddr);
3625
3626 /* Update the error counts. */
3627 tp->stats.rx_missed_errors += RTL_R32(RxMissed);
3628 RTL_W32(RxMissed, 0);
3629
3630 spin_unlock_irq(&tp->lock);
3631
3632 synchronize_irq(dev->irq);
3633
3634 /* Give a racing hard_start_xmit a few cycles to complete. */
3635 synchronize_sched(); /* FIXME: should this be synchronize_irq()? */
3636
3637 /*
3638 * And now for the 50k$ question: are IRQ disabled or not ?
3639 *
3640 * Two paths lead here:
3641 * 1) dev->close
3642 * -> netif_running() is available to sync the current code and the
3643 * IRQ handler. See rtl8169_interrupt for details.
3644 * 2) dev->change_mtu
3645 * -> rtl8169_poll can not be issued again and re-enable the
3646 * interruptions. Let's simply issue the IRQ down sequence again.
3647 *
3648 * No loop if hotpluged or major error (0xffff).
3649 */
3650 intrmask = RTL_R16(IntrMask);
3651 if (intrmask && (intrmask != 0xffff))
3652 goto core_down;
3653
3654 rtl8169_tx_clear(tp);
3655
3656 rtl8169_rx_clear(tp);
3657 }
3658
3659 static int rtl8169_close(struct net_device *dev)
3660 {
3661 struct rtl8169_private *tp = netdev_priv(dev);
3662 struct pci_dev *pdev = tp->pci_dev;
3663
3664 rtl8169_down(dev);
3665
3666 free_irq(dev->irq, dev);
3667
3668 pci_free_consistent(pdev, R8169_RX_RING_BYTES, tp->RxDescArray,
3669 tp->RxPhyAddr);
3670 pci_free_consistent(pdev, R8169_TX_RING_BYTES, tp->TxDescArray,
3671 tp->TxPhyAddr);
3672 tp->TxDescArray = NULL;
3673 tp->RxDescArray = NULL;
3674
3675 return 0;
3676 }
3677
3678 static void rtl_set_rx_mode(struct net_device *dev)
3679 {
3680 struct rtl8169_private *tp = netdev_priv(dev);
3681 void __iomem *ioaddr = tp->mmio_addr;
3682 unsigned long flags;
3683 u32 mc_filter[2]; /* Multicast hash filter */
3684 int rx_mode;
3685 u32 tmp = 0;
3686
3687 if (dev->flags & IFF_PROMISC) {
3688 /* Unconditionally log net taps. */
3689 if (netif_msg_link(tp)) {
3690 printk(KERN_NOTICE "%s: Promiscuous mode enabled.\n",
3691 dev->name);
3692 }
3693 rx_mode =
3694 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
3695 AcceptAllPhys;
3696 mc_filter[1] = mc_filter[0] = 0xffffffff;
3697 } else if ((dev->mc_count > multicast_filter_limit)
3698 || (dev->flags & IFF_ALLMULTI)) {
3699 /* Too many to filter perfectly -- accept all multicasts. */
3700 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
3701 mc_filter[1] = mc_filter[0] = 0xffffffff;
3702 } else {
3703 struct dev_mc_list *mclist;
3704 unsigned int i;
3705
3706 rx_mode = AcceptBroadcast | AcceptMyPhys;
3707 mc_filter[1] = mc_filter[0] = 0;
3708 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
3709 i++, mclist = mclist->next) {
3710 int bit_nr = ether_crc(ETH_ALEN, mclist->dmi_addr) >> 26;
3711 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
3712 rx_mode |= AcceptMulticast;
3713 }
3714 }
3715
3716 spin_lock_irqsave(&tp->lock, flags);
3717
3718 tmp = rtl8169_rx_config | rx_mode |
3719 (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
3720
3721 if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
3722 u32 data = mc_filter[0];
3723
3724 mc_filter[0] = swab32(mc_filter[1]);
3725 mc_filter[1] = swab32(data);
3726 }
3727
3728 RTL_W32(MAR0 + 0, mc_filter[0]);
3729 RTL_W32(MAR0 + 4, mc_filter[1]);
3730
3731 RTL_W32(RxConfig, tmp);
3732
3733 spin_unlock_irqrestore(&tp->lock, flags);
3734 }
3735
3736 /**
3737 * rtl8169_get_stats - Get rtl8169 read/write statistics
3738 * @dev: The Ethernet Device to get statistics for
3739 *
3740 * Get TX/RX statistics for rtl8169
3741 */
3742 static struct net_device_stats *rtl8169_get_stats(struct net_device *dev)
3743 {
3744 struct rtl8169_private *tp = netdev_priv(dev);
3745 void __iomem *ioaddr = tp->mmio_addr;
3746 unsigned long flags;
3747
3748 if (netif_running(dev)) {
3749 spin_lock_irqsave(&tp->lock, flags);
3750 tp->stats.rx_missed_errors += RTL_R32(RxMissed);
3751 RTL_W32(RxMissed, 0);
3752 spin_unlock_irqrestore(&tp->lock, flags);
3753 }
3754
3755 return &tp->stats;
3756 }
3757
3758 #ifdef CONFIG_PM
3759
3760 static int rtl8169_suspend(struct pci_dev *pdev, pm_message_t state)
3761 {
3762 struct net_device *dev = pci_get_drvdata(pdev);
3763 struct rtl8169_private *tp = netdev_priv(dev);
3764 void __iomem *ioaddr = tp->mmio_addr;
3765
3766 if (!netif_running(dev))
3767 goto out_pci_suspend;
3768
3769 netif_device_detach(dev);
3770 netif_stop_queue(dev);
3771
3772 spin_lock_irq(&tp->lock);
3773
3774 rtl8169_asic_down(ioaddr);
3775
3776 tp->stats.rx_missed_errors += RTL_R32(RxMissed);
3777 RTL_W32(RxMissed, 0);
3778
3779 spin_unlock_irq(&tp->lock);
3780
3781 out_pci_suspend:
3782 pci_save_state(pdev);
3783 pci_enable_wake(pdev, pci_choose_state(pdev, state),
3784 (tp->features & RTL_FEATURE_WOL) ? 1 : 0);
3785 pci_set_power_state(pdev, pci_choose_state(pdev, state));
3786
3787 return 0;
3788 }
3789
3790 static int rtl8169_resume(struct pci_dev *pdev)
3791 {
3792 struct net_device *dev = pci_get_drvdata(pdev);
3793
3794 pci_set_power_state(pdev, PCI_D0);
3795 pci_restore_state(pdev);
3796 pci_enable_wake(pdev, PCI_D0, 0);
3797
3798 if (!netif_running(dev))
3799 goto out;
3800
3801 netif_device_attach(dev);
3802
3803 rtl8169_schedule_work(dev, rtl8169_reset_task);
3804 out:
3805 return 0;
3806 }
3807
3808 #endif /* CONFIG_PM */
3809
3810 static struct pci_driver rtl8169_pci_driver = {
3811 .name = MODULENAME,
3812 .id_table = rtl8169_pci_tbl,
3813 .probe = rtl8169_init_one,
3814 .remove = __devexit_p(rtl8169_remove_one),
3815 #ifdef CONFIG_PM
3816 .suspend = rtl8169_suspend,
3817 .resume = rtl8169_resume,
3818 #endif
3819 };
3820
3821 static int __init rtl8169_init_module(void)
3822 {
3823 return pci_register_driver(&rtl8169_pci_driver);
3824 }
3825
3826 static void __exit rtl8169_cleanup_module(void)
3827 {
3828 pci_unregister_driver(&rtl8169_pci_driver);
3829 }
3830
3831 module_init(rtl8169_init_module);
3832 module_exit(rtl8169_cleanup_module);
3833
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