1 /*
2 * pata_ninja32.c - Ninja32 PATA for new ATA layer
3 * (C) 2007 Red Hat Inc
4 * Alan Cox <alan@redhat.com>
5 *
6 * Note: The controller like many controllers has shared timings for
7 * PIO and DMA. We thus flip to the DMA timings in dma_start and flip back
8 * in the dma_stop function. Thus we actually don't need a set_dmamode
9 * method as the PIO method is always called and will set the right PIO
10 * timing parameters.
11 *
12 * The Ninja32 Cardbus is not a generic SFF controller. Instead it is
13 * laid out as follows off BAR 0. This is based upon Mark Lord's delkin
14 * driver and the extensive analysis done by the BSD developers, notably
15 * ITOH Yasufumi.
16 *
17 * Base + 0x00 IRQ Status
18 * Base + 0x01 IRQ control
19 * Base + 0x02 Chipset control
20 * Base + 0x03 Unknown
21 * Base + 0x04 VDMA and reset control + wait bits
22 * Base + 0x08 BMIMBA
23 * Base + 0x0C DMA Length
24 * Base + 0x10 Taskfile
25 * Base + 0x18 BMDMA Status ?
26 * Base + 0x1C
27 * Base + 0x1D Bus master control
28 * bit 0 = enable
29 * bit 1 = 0 write/1 read
30 * bit 2 = 1 sgtable
31 * bit 3 = go
32 * bit 4-6 wait bits
33 * bit 7 = done
34 * Base + 0x1E AltStatus
35 * Base + 0x1F timing register
36 */
37
38 #include <linux/kernel.h>
39 #include <linux/module.h>
40 #include <linux/pci.h>
41 #include <linux/init.h>
42 #include <linux/blkdev.h>
43 #include <linux/delay.h>
44 #include <scsi/scsi_host.h>
45 #include <linux/libata.h>
46
47 #define DRV_NAME "pata_ninja32"
48 #define DRV_VERSION "0.0.1"
49
50
51 /**
52 * ninja32_set_piomode - set initial PIO mode data
53 * @ap: ATA interface
54 * @adev: ATA device
55 *
56 * Called to do the PIO mode setup. Our timing registers are shared
57 * but we want to set the PIO timing by default.
58 */
59
60 static void ninja32_set_piomode(struct ata_port *ap, struct ata_device *adev)
61 {
62 static u16 pio_timing[5] = {
63 0xd6, 0x85, 0x44, 0x33, 0x13
64 };
65 iowrite8(pio_timing[adev->pio_mode - XFER_PIO_0],
66 ap->ioaddr.bmdma_addr + 0x1f);
67 ap->private_data = adev;
68 }
69
70
71 static void ninja32_dev_select(struct ata_port *ap, unsigned int device)
72 {
73 struct ata_device *adev = &ap->link.device[device];
74 if (ap->private_data != adev) {
75 iowrite8(0xd6, ap->ioaddr.bmdma_addr + 0x1f);
76 ata_sff_dev_select(ap, device);
77 ninja32_set_piomode(ap, adev);
78 }
79 }
80
81 static struct scsi_host_template ninja32_sht = {
82 ATA_BMDMA_SHT(DRV_NAME),
83 };
84
85 static struct ata_port_operations ninja32_port_ops = {
86 .inherits = &ata_bmdma_port_ops,
87 .sff_dev_select = ninja32_dev_select,
88 .cable_detect = ata_cable_40wire,
89 .set_piomode = ninja32_set_piomode,
90 };
91
92 static int ninja32_init_one(struct pci_dev *dev, const struct pci_device_id *id)
93 {
94 struct ata_host *host;
95 struct ata_port *ap;
96 void __iomem *base;
97 int rc;
98
99 host = ata_host_alloc(&dev->dev, 1);
100 if (!host)
101 return -ENOMEM;
102 ap = host->ports[0];
103
104 /* Set up the PCI device */
105 rc = pcim_enable_device(dev);
106 if (rc)
107 return rc;
108 rc = pcim_iomap_regions(dev, 1 << 0, DRV_NAME);
109 if (rc == -EBUSY)
110 pcim_pin_device(dev);
111 if (rc)
112 return rc;
113
114 host->iomap = pcim_iomap_table(dev);
115 rc = pci_set_dma_mask(dev, ATA_DMA_MASK);
116 if (rc)
117 return rc;
118 rc = pci_set_consistent_dma_mask(dev, ATA_DMA_MASK);
119 if (rc)
120 return rc;
121 pci_set_master(dev);
122
123 /* Set up the register mappings */
124 base = host->iomap[0];
125 if (!base)
126 return -ENOMEM;
127 ap->ops = &ninja32_port_ops;
128 ap->pio_mask = 0x1F;
129 ap->flags |= ATA_FLAG_SLAVE_POSS;
130
131 ap->ioaddr.cmd_addr = base + 0x10;
132 ap->ioaddr.ctl_addr = base + 0x1E;
133 ap->ioaddr.altstatus_addr = base + 0x1E;
134 ap->ioaddr.bmdma_addr = base;
135 ata_sff_std_ports(&ap->ioaddr);
136
137 iowrite8(0x05, base + 0x01); /* Enable interrupt lines */
138 iowrite8(0xBE, base + 0x02); /* Burst, ?? setup */
139 iowrite8(0x01, base + 0x03); /* Unknown */
140 iowrite8(0x20, base + 0x04); /* WAIT0 */
141 iowrite8(0x8f, base + 0x05); /* Unknown */
142 iowrite8(0xa4, base + 0x1c); /* Unknown */
143 iowrite8(0x83, base + 0x1d); /* BMDMA control: WAIT0 */
144 /* FIXME: Should we disable them at remove ? */
145 return ata_host_activate(host, dev->irq, ata_sff_interrupt,
146 IRQF_SHARED, &ninja32_sht);
147 }
148
149 static const struct pci_device_id ninja32[] = {
150 { 0x1145, 0xf021, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
151 { 0x1145, 0xf024, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
152 { },
153 };
154
155 static struct pci_driver ninja32_pci_driver = {
156 .name = DRV_NAME,
157 .id_table = ninja32,
158 .probe = ninja32_init_one,
159 .remove = ata_pci_remove_one
160 };
161
162 static int __init ninja32_init(void)
163 {
164 return pci_register_driver(&ninja32_pci_driver);
165 }
166
167 static void __exit ninja32_exit(void)
168 {
169 pci_unregister_driver(&ninja32_pci_driver);
170 }
171
172 MODULE_AUTHOR("Alan Cox");
173 MODULE_DESCRIPTION("low-level driver for Ninja32 ATA");
174 MODULE_LICENSE("GPL");
175 MODULE_DEVICE_TABLE(pci, ninja32);
176 MODULE_VERSION(DRV_VERSION);
177
178 module_init(ninja32_init);
179 module_exit(ninja32_exit);
180
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